A semiconductor device includes a semiconductor part and first to fourth electrodes. The semiconductor part includes a first layer of a first conductivity type and second and third layers of a second conductivity type. The first and second electrodes are provided on back and front surfaces of the semiconductor part, respectively. The third electrode is provided inside a trench of the semiconductor part. The fourth electrode is provided on the front surface of the semiconductor part. The first layer extends between the first electrode and the second and fourth electrodes. The second layer is provided between the first layer and the second electrode. The third layer is provided between the first layer and the fourth electrode. The third electrode includes an end provided between the third layer and the fourth electrode. The third layer is electrically connected to the second electrode via the third and fourth electrodes.

A semiconductor module includes: a first power semiconductor element that includes a first main current electrode; a main body that accommodates therein the first power semiconductor element; and a first main current terminal connectable to the first main current electrode. The main body includes: a top face; a side face that connects to the top face; a bottom face fixable to a cooler; and a recessed portion that is on the side face, and accommodates therein an end portion of an insulating member. The first main current terminal protrudes from the side face of the main body, and includes: a first face; and a second face on an opposite side of the first face. The second face is closer to the bottom face than the first face on the side face. The recessed portion is on the side face between the bottom face and the second face, and is at a position apart from the bottom face.

A power device which is formed on a semiconductor substrate includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode and a clamp diode. The PN diode is connected in parallel to the LIGBT. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a drain and a gate of the LIGBT, to clamp a gate voltage applied to the gate not to be higher than a predetermined voltage threshold.

A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.

A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and within 100 μm at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of metal same with a metal contained in the lower layer of the lower electrode.

A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.

An interlayer insulating film includes a first insulating film formed on a semiconductor layer and a second insulating film formed on the first insulating film. The first insulating film is a silicon oxide film and the second insulating film is a BPSG film. A thickness of the second insulating film is larger than a thickness of the first insulating film. A contact hole is formed of a first contact hole and a second contact hole. The first contact hole penetrates an emitter region and reaches a base region. The second contact hole is formed in the first insulating film and the second insulating and communicates with the first contact hole. An opening width of the second contact hole is larger than an opening width of the first contact hole.

A display substrate is provided. The display substrate includes a gate electrode disposed on a base; a gate insulating layer disposed on the base and covering the gate electrode; a semiconductor layer disposed on the gate insulating layer and overlapping the gate electrode; a source electrode and a drain electrode disposed on the semiconductor layer and connected to the semiconductor layer; a pixel electrode disposed on the gate insulating layer, connected to the drain electrode, and extending from the drain electrode; a common electrode insulated from the pixel electrode and overlapping the pixel electrode; and a semiconductor pattern disposed between the gate insulating layer and the pixel electrode, the semiconductor pattern overlapping the pixel electrode. The semiconductor pattern comprises a same material as the semiconductor layer and extends from the semiconductor layer.