A semiconductor device includes: a semiconductor substrate including a first surface and a second surface facing each other and including a first semiconductor material; a plurality of fin structures upwardly extending on the first surface of the semiconductor substrate, spaced apart from each other by a plurality of trenches, and including the first semiconductor material as the semiconductor substrate; an insulating layer on the first surface of the semiconductor substrate filling at least a portion of the plurality of trenches; a gate electrode layer between the plurality of fin structures and surrounded by the insulating layer; a first conductive layer covering the plurality of fin structures; a second conductive layer on the second surface of the semiconductor substrate; and a shield layer between the gate electrode layer and the semiconductor substrate, surrounded by the insulating layer, and electrically connected to the second conductive layer.

A vertical field-effect transistor. The vertical field-effect transistor includes: a drift region, a semiconductor fin on or above the drift region, and a source/drain electrode on or above the semiconductor fin. The semiconductor fin includes at least one concave side wall in the region between the drift region and the source/drain electrode.

In a first aspect of a present inventive subject matter, a method of etching an object to be etched with an etching liquid that contains bromine, and the object contains at least gallium and/or aluminum.

A vertical field effect transistor. The vertical field effect transistor includes: a drift area; a semiconductor fin on or above the drift area; a connection area on or above the semiconductor fin; and a gate electrode, which is formed adjacent to at least one side wall of the semiconductor fin, the semiconductor fin, in a first section, which is situated laterally adjacent to the gate electrode, having a lesser lateral extension than in a second section, which contacts the drift area, and/or than in a third section, which contacts the connection area.

The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

There is provided a semiconductor device including: an n-type semiconductor substrate having a first main surface and a second main surface on an opposite side of the first main surface; an n-type semiconductor layer arranged on the first main surface of the semiconductor substrate; a pair of trenches formed at a distance from each other on a surface of the semiconductor layer on an opposite side of the semiconductor substrate; a pair of gate electrodes buried in the pair of trenches; a gate insulating film interposed between the gate electrodes and the semiconductor layer; a source electrode formed on the surface of the semiconductor layer on the opposite side of the semiconductor substrate; and a drain electrode formed on the second main surface of the semiconductor substrate.

A radio frequency (RF) switch device includes a semiconductor substrate, doped with an impurity of a first conductivity type at a first doping concentration level, and a mesa extending vertically from an upper surface of the substrate and formed contiguous therewith. The mesa includes a drift region doped with the impurity of the first conductivity type at a second doping concentration level, the second doping concentration level being less than the first doping concentration level. The mesa forms a primary current conduction path in the RF switch device. The RF switch device further includes an insulator layer disposed on at least a portion of the upper surface of the substrate and sidewalls of the mesa, and at least one gate disposed on at least a portion of an upper surface of the insulator layer, the gate at least partially surrounding the mesa.

A field-effect transistor includes an n-type semiconductor layer that includes a Ga.sub.2O.sub.3-based single crystal and a plurality of trenches opening on one surface, a gate electrode buried in each of the plurality of trenches, a source electrode connected to a mesa-shaped region between adjacent trenches in the n-type semiconductor layer, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on an opposite side to the source electrode.

A semiconductor device manufacturing method of embodiments includes: performing first ion implantation implanting an element of either carbon (C) or oxygen (O) into a nitride semiconductor layer; performing second ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a coating layer on a surface of the nitride semiconductor layer; performing a first heat treatment; removing the coating layer; and performing a second heat treatment.

The present disclosure provides a gallium oxide semiconductor structure, a vertical gallium oxide-based power device, and a preparation method. An unintentionally doped gallium oxide layer (110) is transferred to a highly doped and highly thermally conductive heterogeneous substrate (200) by bonding and thinning; then a heavily doped gallium oxide layer (120) is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure including the heterogeneous substrate (200), the gallium oxide layer (110), and the heavily doped gallium oxide layer (120) stacked in sequence. In the vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure, the gallium oxide layer (110) is a thicker intermediate layer and a carrier concentration of the gallium oxide layer (110) is less than that of the heavily doped gallium oxide layer (120). Therefore, the breakdown voltage of the device is also increased through structural design. The highly thermally conductive heterogeneous substrate (200) improves the heat dissipation performance of the device. The device with multiple Fin structures provides a large amount of current.