A highly flexible display device and a method for manufacturing the display device are provided. A transistor including a light-transmitting semiconductor film, a capacitor including a first electrode, a second electrode, and a dielectric film between the first electrode and the second electrode, and a first insulating film covering the semiconductor film are formed over a flexible substrate. The capacitor includes a region where the first electrode and the dielectric film are in contact with each other, and the first insulating film does not cover the region.

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Embodiments of the disclosure provide a thin-film transistor, an array substrate, a display panel and a display device. The thin-film transistor includes a current enhancement portion, and the current enhancement portion is provided between a drain and a source. The current enhancement portion may include at least one protrusion portion, and the protrusion portion is provided on the drain and/or the source and faces a channel. The current enhancement portion may include an island portion provided between the drain and the source, and the island portion is separate from the drain and the source. The island portion may include at least one protrusion end, and the at least one protrusion end faces the drain and/or the source.

A semiconductor device include a substrate having a gate area and a contact area, a buried insulating layer formed over the substrate, a fin-type insulating pattern formed over the buried insulating layer and extending in a first horizontal direction, a lower metal layer covering an upper surface and side surfaces of the fin-type insulating pattern in the contact pattern, a channel layer covering an upper surface and side surfaces of the lower metal layer in the contact area and covering the upper surface and the side surfaces of the fin-type insulating pattern in the gate area, a gate pattern disposed over the channel layer in the gate area and extending in a second direction, and a source/drain contact pattern disposed over the channel layer in the contact area. The lower metal layer includes a Ti-based metal. The channel layer includes an oxide semiconductor material.

Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device with stable electrical characteristics is provided. A semiconductor device includes a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order over the first insulating layer. The second insulating layer has a stacked-layer structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order. The first insulating film, the second insulating film, and the third insulating film each contain an oxide. The first insulating film includes a portion in contact with the semiconductor layer. The semiconductor layer contains indium, gallium, and oxygen and includes a region with an indium content percentage higher than a gallium content percentage.

A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

A self-healing field-effect transistor (FET) device is disclosed in this application, the self-healing FET has a self-healing substrate, a self-healing dielectric layer, a gate electrode, at least one source electrode, at least one drain electrode, and at least one channel. The self-healing substrate and the self-healing dielectric layer have a disulfide-containing poly(urea-urethane) (PUU) polymer. The self-healing dielectric layer has a thickness of less than about 10 .Math.m. The electrodes have electrically conductive elongated nanostructures. The at least one channel has semi-conducting elongated nanostructures.

A semiconductor device includes a chip and an electrode that has a laminated structure including a Ti film, a TiN film, a TiAl alloy film and an Al-based metal film that are laminated in that order from the chip side.