A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al.sub.2O.sub.3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al.sub.2O.sub.3—HfO.sub.2. Additional examples are from the group consisting of ZrO.sub.2, HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2, ZrTiO.sub.2, HfTiO.sub.2, La.sub.2O.sub.3, Y.sub.2O.sub.3, Ga.sub.2O.sub.3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.

Provided is a synaptic device including a substrate, a channel layer on the substrate, a gate dielectric layer on the channel layer; and a gate electrode on the gate dielectric layer, wherein the gate dielectric layer includes a charge supply dielectric film and a piezoelectric film, wherein the charge supply dielectric film includes a metal oxide or metal sulfide, wherein the piezoelectric film includes a piezoelectric material that converts a pressure stimulation into an electrical signal, wherein accordance to a change in a signal applied to the gate electrode, a magnitude and aspect of a current flowing through the channel layer are changed.

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

A flexible display motherboard and a manufacturing method thereof are provided. The flexible display motherboard includes a carrier substrate and a flexible display panel unit formed thereon. The flexible display panel unit includes a flexible base formed on the carrier substrate, and a display region and a periphery region which are positioned on the flexible base. A display device is formed in the display region, and the periphery region surrounds the display region. The flexible display panel unit further includes a dissolvable layer positioned between the carrier substrate and the flexible base. The dissolvable layer is formed at least in an area corresponding to the display region. The dissolvable layer is dissolvable in a solvent.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

The present disclosure discloses a method for preparing electrode including: providing a substrate; forming a buffer layer on the substrate; forming a patterned photoresist on the surface of the buffer layer away from the substrate, the photoresist has a bottom surface and a top surface disposed opposite and a side connected between the bottom surface and the top surface, the bottom surface is bonded to the buffer layer; by dry etching, the portions of the photoresist not covered by the buffer layer is removed to form a receiving area; depositing a conductive film, the conductive film layer includes a waste material forming on the top surface and an electrode filling in the receiving area; and stripping the waste material and the photoresist. The yields of the method for preparing electrode of the present disclosure is high.

An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include a back-bias metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the back-bias metallization. The integrated RF circuit structure may further include a handle substrate on a front-side dielectric layer on the active device.

Provided are a nano-structure assembly including an insulating substrate; and a nano-structure formed on the insulating substrate, and a nano-device including the same.

Embodiments of the present invention relate to a thin film transistor array panel and a display device including the same. An exemplary embodiment of the present invention provides a thin film transistor array panel and a display device including the same, including: an insulation substrate including an upper surface and a lower surface; a light blocking member disposed on or facing the upper surface of the insulation substrate and defining a plurality of openings; and a thin film transistor disposed on the upper surface of the insulation substrate. The insulation substrate may include a plurality of recesses formed in the opening in the lower surface of the insulation substrate, each recess positioned to correspond to one of the openings.

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.