Disclosed are a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), a method for fabricating the same, an array substrate, a display panel, and a display device. The LTPS TFT includes an active layer, a source, a drain, a gate, and a gate insulating layer which are arranged on a substrate. The gate insulating layer is arranged between the active layer and the gate, and a graphene oxide layer which is arranged between the active layer and the gate insulating layer. Since the graphene oxide layer is arranged between the active layer and the gate insulating layer, the interface between the active layer and the gate insulating layer of polycrystalline (P-Si) has a reduced roughness and interfacial defect density, and a pre-cleaning process is not necessary for the gate insulating layer.

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

Provided is a semiconductor device including a first insulator, a second insulator, a first oxide semiconductor, a second oxide semiconductor, a first conductor, and a second conductor. The first oxide semiconductor is over the first insulator. The second oxide semiconductor is over the first oxide semiconductor. The first conductor includes a region in contact with a top surface of the second oxide semiconductor. The second insulator includes a region in contact with the top surface of the second oxide semiconductor. The second conductor is over the second oxide semiconductor with the second insulator therebetween. The second oxide semiconductor includes a first layer and a second layer. The first layer includes a region in contact with the first oxide semiconductor. The second layer includes a region in contact with the second insulator. The first layer has a lower proportion of oxygen vacancies than the second layer.

A display device includes a buffer layer disposed on a substrate and comprising a first buffer film, and a second buffer film, wherein the first buffer film and the second buffer film are sequentially stacked in a thickness direction of the display device; a semiconductor pattern disposed on the buffer layer; a gate insulating layer disposed on the semiconductor pattern; and a gate electrode disposed on the gate insulating layer, wherein the first buffer film and the second buffer film comprise a same material, and a density of the first buffer film is greater than a density of the second buffer film.

Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.

A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an insulating material. A bottom layer is positioned between the substrate and the buffer layer. The bottom layer and the semiconductor layer overlap each other. The bottom layer includes a first layer, a second layer, and a third layer that are stacked on each other in a direction away from the substrate.

A transistor with a small footprint is provided. A transistor having high reliability is provided. A transistor is provided over an insulating layer that has a projection. Over the projection, at least a channel formation region of a semiconductor layer is provided. This can reduce the footprint of the transistor. The transistor has a curved structure, which inhibits light that enters from the outside from reaching a channel formation region of the semiconductor layer. Accordingly, deterioration of the transistor due to external light can be reduced, whereby the transistor can have increased reliability. The projection can be obtained by utilizing the internal stress of the layer formed over the insulating layer. Alternatively, the projection can be obtained by placing, under the insulating layer, a structure body for providing the insulating layer with the projection.

According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.

In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×10.sup.20 atoms/cm.sup.3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

A method device is prepared with a patterned thin film that can include one or more metal oxides on a suitable substrate. Initially, a pattern of a deposition inhibitor is provided on a surface of the substrate, which deposition inhibitor comprises at least one cellulose ester. This pattern has both inhibitor areas where the deposition inhibitor is present and open areas where the deposition inhibitor is absent. An inorganic thin film is then deposited on the surface of the substrate by a chemical vapor deposition process only in the open areas of the pattern. Further operations can be carried out including deposit of a second inorganic thin film exactly over the initial inorganic thin film, the deposition inhibitor can be removed from the inhibitor areas of the pattern, or both operations can be carried out in sequence.