A thin film transistor array panel includes a substrate, a gate line and a gate pad disposed on the substrate, a gate insulating layer disposed on the gate line and the gate pad, a data line and a data pad disposed on the gate insulating layer, an organic layer disposed on the data line and the data pad, and a connecting member disposed on one of the gate pad and the data pad, in which the organic layer includes a first portion overlapping the connecting member and a second portion not overlapping the connecting member, and a height of the first portion of the organic layer is greater than a height of the second portion of the organic layer.

A thin film transistor (TFT) substrate includes a substrate and a TFT. The TFT is disposed on the substrate and comprises a gate, a gate dielectric layer, a film, a source and a drain. The gate is disposed on the substrate. The gate dielectric layer is disposed on the gate and the substrate. The film is disposed above the gate dielectric layer, and the source and the drain are disposed on the film and contacts with the film respectively. Wherein, there is an interval between the source and the drain, and the film corresponding to the interval has an arc concave portion. In addition, a display panel is also disclosed.

An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.

The present disclosure relates to a thin film transistor substrate having a high reliability oxide semiconductor material including a metal oxide semiconductor material. A thin film transistor substrate includes a substrate, a gate electrode disposed on the substrate, a semiconductor layer including an oxide semiconductor material combining one or more of indium, gallium and zinc, oxygen, and a doping material. The doping material may be a group 15 or 16 gaseous element. The semiconductor layer has a channel area overlapping with the gate electrode with a gate insulating layer, a source area extended from one side of the channel area, and a drain area extended from another side of the channel area, a source electrode connected to the source area, and a drain electrode connected to the drain area.

The present application discloses a array substrate, a manufacturing method of the array substrate, and a display panel, the manufacture procedure includes the following steps: sequentially forming a buffer layer and a photoresist layer on a glass substrate; placing the substrate into an activation agent for activation, and forming an activation liquid particle layer with a first preset pattern at a corresponding position where the activation agent is in contact with the photoresist layer, and forming an activation liquid particle layer with a second preset pattern at a corresponding position where the activation agent is in contact with the buffer layer; removing the photoresist layer and the activation liquid particle layer with the first preset pattern; and performing chemical plating to form a first metal layer at a position corresponding to the activation liquid particle layer with the second preset pattern in contact with the buffer layer.

A stacked structure includes: an insulating substrate; a graphene film that is formed on the insulating substrate; and a protective film that is formed on the graphene film and is made of a transition metal oxide, which is, for example, Cr.sub.2O.sub.3. Thereby, at the time of transfer of the graphene, polymeric materials such as a resist are prevented from directly coming into contact with the graphene and nonessential carrier doping on the graphene caused by a polymeric residue of the resist is suppressed.

Disclosed is a graphene transistor using graphene as a channel region and a logic device using the same. A doping metal layer is provided over a graphene channel of the graphene transistor. The doping metal layer has a work function higher or lower than that of the graphene. When the doping metal layer has a work function lower than that of the graphene, the graphene, which is below the doping metal layer, is doped with an n-type. Also, when the doping metal layer has a work function higher than that of the graphene, the graphene, which is below the doping metal layer, is doped with a p-type. As described above, various aspects of junction may be implemented in the graphene channel, and three states may be obtained from a single transistor.

A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

A display device including a plurality of thin film transistors. One of the plurality of thin film transistors includes a gate electrode, a semiconductor layer having a region overlapping the gate electrode, a gate insulating layer between the gate electrode and the semiconductor layer, a source electrode and a drain electrode in contact with a surface of the semiconductor layer opposite to the side of the gate insulating layer, and a first shield electrode arranged in a region where the source electrode and the gate electrode overlap, and a second shield electrode arranged in a region where the drain electrode and the gate electrode overlap. The first shield electrode and the second shield electrode are arranged between the gate electrode and the semiconductor layer, and are insulated from the gate electrode, the semiconductor layer, the source electrode, and the drain electrode.