The disclosure provides a thin film transistor, a method of manufacturing the thin film transistor, an array substrate and a display device, belongs to the field of display technology, and can solve the problem that an existing thin film transistor is prone to cracking or breaking due to bending. The thin film transistor of the present disclosure includes a substrate and an active layer arranged on the substrate, and at least one groove is arranged on a surface of the active layer distal to the substrate.

An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate.

A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

One example provides an integrated circuit comprising a transistor including a semiconductor channel. The semiconductor channel includes three or more sub-channels, one or more nodes, each node being a junction of at least three sub-channels, and channel ends. A Schottky contact at each channel end forms a source or drain contact, and a gate contact disposed at each Schottky contact controls a barrier conductivity of the corresponding Schottky contact.

A display device includes, in a display area: scan control lines and data signal lines intersecting with each other; subpixels each including a subpixel circuit provided at an intersection of the scan control lines and the data signal lines; and light-emitting elements, one for each of the subpixels. The subpixel circuit includes a drive transistor, a write transistor, and a capacitor that retains a data signal. The write transistor includes a conduction terminal connected to an associated one of the data signal lines, another conduction terminal connected to a first gate terminal of the drive transistor, and a control terminal connected to an associated one of the scan control lines. Each of the light-emitting elements includes a first element electrode, a light-emitting layer, and a second element electrode, the first element electrode being connected to a conduction terminal of the drive transistor. The drive transistor includes a second gate terminal connected to the second element electrode via a contact hole.

A semiconductor device in which variation of characteristics is small is provided. A second insulator, an oxide, a conductive layer, and an insulating layer are formed over a first insulator; a third insulator and fourth insulator are deposited to be in contact with the first insulator; a first opening reaching the oxide is formed in the conductive layer, the insulating layer, the third insulator, and the fourth insulator; a fifth insulator, a sixth insulator, and a conductor are formed in the first opening; a seventh insulator is deposited over the fourth insulator, the fifth insulator, and the sixth insulator; a mask is formed in a first region over the seventh insulator in a top view; oxygen is implanted into a second region not overlapping the first region in the top view; heat treatment is performed; a second opening reaching the fourth insulator is formed in the seventh insulator; and heat treatment is performed.

Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

A thin-film transistor substrate includes: a substrate; a semiconductor layer on the substrate, where the semiconductor layer includes a first conductive region, a second conductive region, and a first channel region between the first conductive region and the second conductive region; a gate insulating layer on the semiconductor layer, where the gate insulating layer includes a first charge implanted region which overlaps a portion of the first channel region and into which charged ions are implanted; and a first gate electrode on the gate insulating layer to overlap the first channel region. The first charge implanted region is shifted to the first conductive region or the second conductive region.

Provided are an array substrate and a fabrication method therefor, a shift register unit, and a display panel. The array substrate includes a first transistor having a double gate structure, and further includes an active layer arranged on one side of the base substrate and a first conductive layer. The active layer includes a first conductor portion connected between a first semiconductor portion and a second semiconductor portion, the first semiconductor portion and a second semiconductor portion forming a channel region of the first transistor. The first conductive layer includes a first conductive portion connected to a stable voltage source, an orthographic projection of the first conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate, and the first conducting portion and the first conductor portion form two electrodes of a parallel-plate capacitor.