Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate layer between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices.

A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

A drive backplane and a display panel are provided, the drive backplane includes: a substrate; and an oxide thin film transistor arranged on the substrate, wherein the oxide thin film transistor includes: an oxide active layer; a first gate structure disposed on a side of the oxide active layer away from the substrate; and a second gate structure disposed between the oxide active layer and the substrate; wherein at least one of the first gate structure and the second gate structure comprises a plurality of gate electrodes spaced apart along a direction in which the oxide active layer extends.

On a substrate, an N.sup.+ layer connecting to a source line SL, a first Si pillar standing in a perpendicular direction, and a second Si pillar on the first Si pillar are disposed. In a central portion of the first Si pillar, a P.sup.+ layer is disposed, and a P layer is disposed so as to surround the P.sup.+ layer. In a central portion of the second Si pillar, a P.sup.+ layer is disposed, and a P layer is disposed so as to surround the P.sup.+ layer. On the second Si pillar, an N.sup.+ layer is disposed so as to connect to a bit line BL. A first gate insulating layer is disposed so as to surround the first Si pillar, and a second gate insulating layer is disposed so as to surround the second Si pillar. A first gate conductor layer is disposed so as to surround the first insulating layer and to connect to a plate line PL, and a second gate conductor layer is disposed so as to surround the second insulating layer and to connect to a word line WL. Voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled, to perform a data retention operation of retaining a hole group generated within a channel region due to an impact ionization phenomenon or a gate induced drain leakage current and a data erase operation of discharging the hole group from within the channel region.

A thin film transistor and a non-volatile memory device are provided. The thin film transistor comprises a gate electrode, and a metal oxide channel layer traversing the upper or lower portions of the gate electrode. The metal oxide channel layer has semiconductor properties while having bixbyite crystals. An insulating layer is disposed between the gate electrode and the metal oxide channel layer. Source and drain electrodes are electrically connected to both ends of the metal oxide channel layer, respectively.

A thin film transistor, a display panel comprising the same and a display apparatus are discussed. The thin film transistor comprises a buffer layer embodied on a substrate, a semiconductor layer embodied on the buffer layer, including a channel area, a first conductor portion and a second conductor portion, a gate insulating film embodied on the semiconductor layer, a gate electrode embodied on the gate insulating film, and an auxiliary electrode overlapped with the second conductor portion, wherein the first conductor portion is extended from one side of the channel area, and becomes a source area, and the second conductor portion is extended from the other side of the channel area, and becomes a drain area.

Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate including monocrystalline silicon or polycrystalline silicon, a first insulating layer on the semiconductor substrate, the first insulating layer including a local region in which a portion of an upper surface of the first insulating layer is recessed, a channel layer provided in the local region of the first insulating layer, a silicide provided on one side surface of the channel layer, a control gate provided on the channel layer, a gate insulating film provided between the channel layer and the control gate, and a polarity control gate arranged so as to overlap an interface between the channel layer and the silicide, wherein the polarity control gate is spaced apart from the control gate, and the channel layer includes monocrystalline silicon.

A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.

According to one embodiment, a display device includes first semiconductor layers crossing a first scanning line in a non-display area, the first semiconductor layers being a in number, second semiconductor layers crossing a second scanning line in the non-display area, the second semiconductor layers being b in number, and an insulating film disposed between the first and second semiconductor layers and the first and second scanning lines, wherein a and b are integers greater than or equal to 2, and a is different from b, and the first and second semiconductor layers are both entirely covered with the insulating film.

A semiconductor structure is provided having improved electrostatic contact close to the dielectric pillar that separates a first device region from a second device region. The semiconductor structure includes a dielectric pillar located between a first vertical nanosheet stack of suspended semiconductor channel material nanosheets and a second vertical nanosheet stack of suspended semiconductor channel material nanosheets. Horizontal dielectric bridge structures can be located in the first and second device regions. The horizontal bridge structures connect each of the suspended semiconductor channel material nanosheets to a respective sidewall of the dielectric pillar. A dielectric spacer structure can laterally surround a lower portion of the dielectric pillar and be present in a semiconductor substrate. In some embodiments, the horizontal dielectric bridge structures can be omitted.