Devices and methods for switch body connections to achieve soft breakdown. In some embodiments, a field-effect transistor (FET) can include an assembly of source, gate, and drain implemented on an active region, a first body contact implemented at a first end of the assembly, and a second body contact implemented at a second end of the assembly. The second end can be distal from the first end along a width of the field-effect transistor.

A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.

A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

Embodiments of the present invention provide a display panel. The display panel includes a flexible substrate, wherein a first opening is provided at a bottom of the flexible substrate; a first inorganic layer; a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes a silicon semiconductor layer, and the second thin film transistor includes a metal oxide semiconductor layer and a second inorganic layer, wherein the second inorganic layer is provided with a second opening, and the second opening at least partially overlaps the first opening.

In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.

A display device includes a first thin-film transistor (TFT) including a first semiconductor layer including silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a first interlayer insulating layer covering the first gate electrode, a second TFT arranged on the first interlayer insulating layer and including a second semiconductor layer including oxide semiconductor and a second gate electrode insulated from the second semiconductor layer, a second interlayer insulating layer covering the second gate electrode, a first power supply voltage line arranged on the second interlayer insulating layer, a first planarization layer covering the first power supply voltage line, and a data line arranged on the first planarization layer and at least partially overlapping the first power supply voltage line.

A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.

A three-dimensional semiconductor wafer relates to a semiconductor wafer, including a raw semiconductor wafer, at least one connection layer, a conduction layer and a protection layer, wherein the protection layer is arranged on the conduction layer; the connection layer is inserted into a bottom surface or/and a top surface of the raw semiconductor wafer; and the conduction layer is arranged on the bottom surface of the raw semiconductor wafer.

A display panel includes a base layer including a display area and a non-display area, a repair circuit disposed in the non-display area, a pixel disposed in the display area and including a pixel circuit and a light emitting element electrically connected to the pixel circuit, and a repair line electrically connecting the repair circuit to the pixel. The pixel circuit includes a silicon transistor including a silicon semiconductor pattern and a first gate disposed on the silicon semiconductor pattern, an oxide transistor including a light shielding pattern disposed on the first gate and disposed on the same layer as the repair line, an oxide semiconductor pattern disposed on the light shielding pattern, and a second gate disposed on the oxide semiconductor pattern, and a bridge electrode electrically connected to the light emitting element and the silicon transistor.