Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.

An array substrate, a method of manufacturing the same, and a display device are provided. The array substrate includes a first active layer and a second active layer. A material of the first active layer comprises low temperature poly-silicon. A material of the second active layer comprises an oxide semiconductor. The first active layer and the second active layer are disposed at different layers and horizontally staggered.

A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.

Techniques, materials, and structures for stretchable semiconductor nanomesh structures are described. In one embodiment, a stretchable semiconductor nanomesh structure may include a nanomesh formation of certain semiconductor material comprising a network of traces forming at least one opening between sidewalls of the nanomesh formation material, and a substrate configured to support the nanomesh formation material. Other embodiments are described.

In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOD metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.

A display device includes: a substrate; a display area including pixels arranged on the substrate; a first area disposed at one side of the display area; a second area including pads arranged on the substrate; a bending area disposed between the first area and the second area; and a fan-out line disposed in the first area, the bending area, and the second area. The fan-out line includes: a plurality of sub-routing lines arranged in the first area and electrically connected to each other; and a plurality of sub-pad lines arranged in the second area and electrically connected to each other. The number of the plurality of sub-routing lines is greater than the number of the plurality of sub-pad lines.

A display device with high resolution is provided. A display device with low power consumption is provided. A display device with high luminance is provided. A display device with a high aperture ratio is provided. The display device includes a first wiring, a second wiring, a third wiring, and a pixel electrode. The first wiring extends in a first direction and is supplied with a source signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a gate signal. The third wiring is supplied with a constant potential. The first wiring and the pixel electrode overlap with each other with the third wiring therebetween.