An integrated circuit includes a memory array that stores data, a rectifying circuit that rectifies an alternating current and generates a direct-current voltage, and a logic circuit that reads data stored in a memory. The memory array includes a first semiconductor memory element having a first semiconductor layer. The rectifying circuit includes a second semiconductor rectifying element having a second semiconductor layer. The logic circuit includes a third semiconductor logic element having a third semiconductor layer. The second semiconductor layer is a functional layer exhibiting a rectifying action and the third semiconductor layer is a channel layer of a logic element. All the first, second and third semiconductor layers, the functional layer exhibiting a rectifying action and the channel layer are formed of the same material including at least one selected from an organic semiconductor, a carbon nanotube, graphene, or fullerene.

Present invention relates to a semiconductor memory device. A semiconductor memory device according to the present invention may comprise: a memory cell array including a plurality of memory cells over a substrate, the plurality of memory cells repeatedly arranged in horizontal direction and a vertical direction, the horizontal direction parallel to a surface of the substrate, the vertical direction perpendicular to the surface of the substrate, a bit line coupled to the memory cells arranged in the vertical direction, and a word line coupled to the memory cells arranged in the horizontal direction, wherein each of the memory cells comprises a capacitor comprising a storage node and a plate node, and the plate nodes of the capacitors are coupled to each other in the vertical direction and are spaced apart from each other in the horizontal direction.

An electronic device, and method of producing an electronic device, are disclosed. The electronic device comprises a diamond substrate 10. Within the substrate 10 is an electrode 12, known as a ‘buried electrode’. A first surface 14 of the substrate 10 is provided with a conductive contact region 16. The electrode 12 is electrically connected to the contact region 16 by a conductive pillar 18. The electrode, conductive pillar, and contact region comprise modified portions of the diamond substrate, for example comprising at least one of graphitic carbon, amorphous carbon, and a combination of SP2 and SP3 phases of carbon, formed from a portion of diamond substrate.

A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.

Provided are biosensors, systems and related methods of using the biosensors and systems. The biosensor comprises a field-effect transistor (FET) having a crumpled geometry to effectively increase the detection sensitivity of a target molecule in an ionic solution. A FET having a crumpled semiconductor material channel can form a π-π interaction with single stranded DNA (ssDNA) for amplification detection applications. Increasing amount of ssDNA in an amplification reaction solution is incorporated into an amplified double stranded DNA, with increasing amplification, resulting in a lower amount of ssDNA primers. The FET is contacted with the amplified solution to electrically detect an amount of ssDNA primer in the amplified solution, thereby detecting amplification based on a decreased amount of ssDNA bound to the FET. Also provided are biosensors that can detect biomolecules more generally, such as protein, polypeptides, polynucleotides, or small molecules.

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a resistance change layer disposed on the substrate and including a plurality of carbon nanostructures, a channel layer disposed on the resistance change layer, a gate electrode layer disposed on the channel layer, and a source electrode layer and a drain electrode layer disposed to contact portions of the channel layer.

FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

A transistor substrate includes a substrate, a semiconductor layer overlapping the substrate, and a gate electrode overlapping the semiconductor layer. The semiconductor layer includes a channel unit, a conductive unit directly connected to an end of the channel unit, and an edge unit positioned at an edge of the conductive unit. A carbon concentration of the edge unit is higher than each of a carbon concentration of the channel unit and a carbon concentration of the conductive unit.

Provided are a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a substrate, a plurality of word lines extending in a first direction on the substrate, a plurality of ferroelectric patterns respectively provided on the word lines, a blocking insulating film covering the ferroelectric patterns, a plurality of bit line pairs including a first bit line and a second bit line extending in a second direction crossing the word lines and the ferroelectric patterns on the blocking insulating film and intersecting the first direction, and a channel pattern provided between the first bit line and the second bit line of each of the bit line pairs on the blocking insulating film, wherein the channel pattern has an ambipolar conduction characteristic.

A transistor includes a channel layer, a gate stack, and source/drain regions. The channel layer includes a graphene layer and hexagonal boron nitride (hBN) flakes dispersed in the graphene layer. Orientations of the hBN flakes are substantially aligned. The gate stack is over the channel layer. The source/drain regions are aside the gate stack.