A semiconductor apparatus includes first, second and third transistors integrated in a monocrystal chip. Both the first and second transistors are vertical devices, each having a source node, a gate node and a drain node. The source node of the first transistor electrically connects to a primary source pin, the source node of the second transistor to a sample pin, and the gate nodes of the first and the second transistors to a control-gate pin. The third transistor is a vertical JFET with a source node, a control node and a drain node. The source node of the third transistor electrically connects to a charge pin, and the control node of the third transistor to a charge-control pin. All of the drain nodes of the first, second and third transistors are electrically connected to a high-voltage pin.

A vertical FET device includes a semiconductor structure comprising a semiconductor substrate, a first semiconductor layer coupled to the semiconductor substrate, and a second semiconductor layer coupled to the first semiconductor layer. The vertical FET device also includes a plurality of fins. Adjacent fins of the plurality of fins are separated by a trench extending into the second semiconductor layer and each of the plurality of fins includes a channel region disposed in the second semiconductor layer. The vertical FET also includes a gate region extending into a sidewall portion of the channel region of each of the plurality of fins, a source metal structure coupled to the second semiconductor layer, a gate metal structure coupled to the gate region, and a drain contact coupled to the semiconductor substrate.

A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.

A power device includes a packaged semiconductor switch containing first and second series-connected insulated-gate transistors, first and second control terminals electrically connected to the first and second insulated-gate transistors, respectively, first and second current carrying terminals electrically connected to the first and second insulated-gate transistors, respectively, and a voltage-monitoring terminal electrically connected to an internal node shared by first and second current carrying regions within the first and second insulated-gate transistors, respectively. The first and second control terminals can be electrically connected to a gate of the first insulated-gate transistor and a gate of the second insulated-gate transistor, respectively; and the first and second current carrying terminals can be electrically connected to a source of the first insulated-gate transistor and a drain (or collector) of the second insulated-gate transistor. The voltage-monitoring terminal is electrically connected to a drain of the first insulated-gate transistor and a source (or emitter) of the second insulated-gate transistor.

The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

An apparatus includes a unipolar power transistor and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate. The capacitor has a p-n junction. The RC snubber has a resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

Embodiments of the disclosure provide a bandgap reference circuit, including: first and second vertically stacked structures, the first and second vertically stacked structures each including: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region.

A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.