A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

A method for producing a semiconductor arrangement, said method includes fastening a semiconductor on a base element by means of a sintered layer, wherein a side of the sintered layer which faces the base element is configured planar; and perforating a region of the base element, which directly contacts the sinter, wherein the perforating includes generating a plurality of through-openings having a closed border in the region of the base element for adjusting a stiffness of at least a portion of the base element in a targeted manner

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

The present invention relates to a bonding method for connecting a first wafer and a second wafer, wherein firstly a first adhesive layer is deposited onto a surface of the first wafer. Furthermore, a second adhesive layer is deposited onto the first adhesive layer, and the two adhesive layers are structured by way of selective removal of both adhesive layers in at least one predefined region of the first wafer, Moreover, the first wafer is connected to the second wafer by way of pressing a surface of the second wafer onto the second adhesive layer, wherein the second adhesive layer is more flowable that the first adhesive layer on connecting the first wafer to the second wafer.

The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

An electronic device includes: a first semiconductor die having a metal region; a substrate having a plurality of metal regions; a first soldered joint between the metal region of the first semiconductor die and a first metal region of the substrate, the first soldered joint having one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the first semiconductor die and the first metal region of the substrate; and a second semiconductor die soldered to the first or different metal region of the substrate.

Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.