A semiconductor device may include a substrate including a chip region and a pad region, first bonding pads positioned in the chip region, second bonding pads positioned on the first bonding pads and having a front surface connected to the first bonding pads, a first probing pad positioned in the pad region, extending to the chip region, and connected to a rear surface of at least one second bonding pad among the second bonding pads, and a second probing pad positioned neighbor the first probing pad and connected to the rear surface of at least one second bonding pad among the second bonding pads.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. A spacer may be included between the power components. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna can be formed within the substrate. An encapsulant is deposited over the surface of the substrate. An ink material is deposited over the surface of the substrate. The ink material can be a curable epoxy. The ink material is formed as a straight wall, curved wall, stepped wall, stepped convex wall, and such. The ink material can be stacked with a first ink material deposited on the surface of the substrate and a second ink material deposited over the first ink material. A shielding material is disposed over the encapsulant with the ink material blocking progression of the shielding material. An electrical connector is disposed over the surface of the substrate outside the ink material to avoid contact with the shielding material.

Embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. In an embodiment the substrate comprises a passive electrical device. In an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. In an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.

Example methods and apparatus for embedding interconnect bridges having through silicon vias in substrates are disclosed. An example semiconductor package a bridge die disposed in a recess of an underlying substrate, the bridge die including a via that electrically couples a first contact on a first side of the bridge die and a second contact on a second side of the bridge die, the recess extending to a first surface of the underlying substrate; a bond material to electrically and mechanically couple the first contact and an interconnect of the underlying substrate; and a fill material positioned between the first side of the bridge die and the first surface of the underlying substrate.

In an aspect, an apparatus includes a base substrate having a first side and a second side. A first substrate on the first side of the base substrate having a first embedded component disposed in a cavity adjacent the first side of the base substrate. A second substrate is on the second side of the base substrate. A first connection structure is disposed between the first substrate and the base substrate configured to electrically couple the first substrate to the base substrate. A second connection structure is disposed between the second substrate and the base substrate configured to electrically couple the second substrate to the base substrate.

A packaged integrated circuit (IC) including a package substrate. The package substrate includes pins; a first metal layer on the pins; a second metal layer on the first metal layer; vias on the second metal layer; an insulation material covering the pins, the first metal layer, the second metal layer, and the vias, and exposing surfaces of the pins and the vias. The packaged IC further includes a semiconductor die on the package substrate, the semiconductor die having a surface opposing the second metal layer; metal posts coupled between the semiconductor die and the exposed surfaces of the vias; and a mold compound covering the semiconductor die and the metal posts, in which the surface is separated from the second metal layer by the insulation material and the mold compound.

A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.

In a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, CTE mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. The air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.

A method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. The transistor is farther away from the semiconductor substrate than the metal layer. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.