Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.

A semiconductor package includes a first chip, an insulating protection layer, a second chip, a plurality of second conductive bumps and an underfill. The insulating protection layer is disposed on a first active surface of the first chip and includes a concave. Projections of a plurality of first inner pads and a plurality of first outer pads of the first chip projected on the insulating protection layer are located in the concave and out of the concave, respectively. The second chip is flipped on the concave and includes a plurality of second pads. Each of the first inner pads is electrically connected to the corresponding second pad through the corresponding second conductive bump. The underfill is disposed between the concave and the second chip and covers the second conductive bumps.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

A semiconductor device includes an insulated circuit board in which a metal layer is formed on one surface of an insulating board and a semiconductor element having a polygonal shape when viewed in a plan view that is bonded to the metal layer via a bonding material. The metal layer of the insulated circuit board has a recess that exposes the insulating board at a position corresponding to at least one corner of the semiconductor element.

A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.

An apparatus includes a polymer base layer having a surface. A die that includes a fluid manipulation surface that is substantially coplanar with the surface of the polymer base layer. The die includes a control electrode to generate an electric field to perform microfluidic manipulation of fluid across the fluid manipulation surface of the die.

A mechanically-stable and thermally-conductive interface device between a semiconductor die and a package for the die, and related method of fabrication, comprising: a semiconductor die; a package for the die; a surface area-enhancing pattern on the package and/or the die; and die attach materials between the die and the package, the die attach materials attaching the die to the package through an interface provided by the die attach materials; wherein: an effective bonding area between the die attach materials and the package and/or the die is greater with the pattern than without the pattern; and the increase of the effective bonding area simultaneously increases the surface area for thermal transport between the package and/or the die, and the die attach materials; and increases the surface area for stably attaching the at least one of the package and the die to the die attach materials.

The semiconductor device includes at least three semiconductor elements disposed directly or indirectly on a planar member and constituting an upper arm and a lower arm which perform ON and OFF action at mutually differential times; an upper-surface voltage applied region of each semiconductor element is configured to be narrower than an area of the aforementioned whole semiconductor element in planar view; and each semiconductor element is disposed so that the shortest distance between the semiconductor elements constituting the upper arm is formed so as to be longer than the shortest distance between the semiconductor element constituting the upper arm and the semiconductor element constituting the lower arm.