A method for manufacturing a structure includes: supplying an active element provided with a front and rear face connected by a contour; assembling the front face and a main face of a support; filling a space of interconnections between the front face and the main face with glue. The method also includes, before the assembling, forming, by a method other than a plasma method, a first passivation layer covering the contour, and made from a first compound that makes it possible to limit the wetting of said contour by the glue regarding the front face and the main face.

One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.

An electrically non-conducting film (109) comprising an oligomer comprising an arylene or heteroarylene repeating unit is disposed between a chip (105), e.g. a flip-chip, and a functional layer (101), e.g. a printed circuit board, electrically connected to the chip by electrically conducting interconnects (107). The oligomer may be crosslinked.

Disclosed is a semiconductor package comprising a first semiconductor chip on a substrate, a second semiconductor chip between the substrate and the first semiconductor chip, and a spacer between the substrate and the first semiconductor chip. The substrate includes a first substrate pad between the second semiconductor chip and the spacer. The second semiconductor chip includes a chip pad and a signal wire. The spacer includes a first dummy pad on the spacer and a first dummy wire coupled to the first dummy pad. The first dummy pad is adjacent to the second semiconductor chip. The first semiconductor chip is attached to the second semiconductor chip and the spacer by an adhesive layer on the first semiconductor chip. A portion of each of the signal wire and the first dummy wire are in the adhesive layer.

The present application discloses an underfill for chip packaging, including 19-25% of epoxy resin, 55-60% of filler, 15-25% of curing agent and 0.5-0.8% of accelerator in mass percentage, wherein the curing agent includes a polycondensate of paraxylene and dihydroxynaphthalene and a polycondensate of paraxylene and naphthol. Both of the polycondensate of paraxylene and dihydroxynaphthalene and the polycondensate of paraxylene and naphthol are selected to be used in the underfill for chip packaging in the present application, so that the underfill has stronger adhesiveness after being cured. In addition, the present application further provides a chip packaging structure using the underfill.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

A member includes a base material and a conductive layer. The conductive layer conducts heat or electricity. The conductive layer includes a conductive portion and a non-conductive portion. The conductive portion conducts heat or electricity. The conductive portion is disposed on at least one of an upper surface or a lower surface of the non-conductive portion and on a side surface of the non-conductive portion.

A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

The disclosure describes a lidded flip chip package allowing for a thermal interface material (TIM) with fluidity, like a liquid metal, including: a lid, a sealing ring for forming a sealed gap between a flip chip and the lid, a storage tunnel as a reservoir for accepting or releasing a liquid metal from or to the sealed gap, and an injection tunnel for filling a liquid metal into the sealed gap, wherein a self-sealing plug structure is integrated with the storage tunnel and the injection tunnel, the sealed gap is completely filled with a liquid metal, and a portion of the storage tunnel is filled with the same liquid metal and its remaining portion is filled with a gas. The disclosure also describes a method for filling a liquid metal into the lidded flip chip package based on the self-sealing plug structure.

An object of the present invention is to improve assemblability of a power semiconductor device. A power semiconductor device includes a plurality of submodules that includes a semiconductor element interposed between a source conductor and a drain conductor, a sense wiring that transmits a sense signal of the semiconductor element, and an insulating portion at which the sense wiring and the sense conductor are arranged, and a source outer conductor that is formed to surround the source conductor and is joined to the source conductor in each of the plurality of submodules. Each source conductor included in the plurality of submodules includes protrusion portions that are formed toward the sensor wiring from the source conductor, are connected to the sense wiring, and define a distance between the sense wiring and the source outer conductor.