A semiconductor device is configured to include: a base member of a semiconductor material which forms a thin plate shape; a front face electrode which is placed on a front surface of the base member; a rear face electrode which covers a rear surface of the base member; and a via hole which forms a hole shape provided with the front face electrode as a bottom and being open onto the rear surface, and through which the front face electrode and the rear face electrode are electrically connected to each other; wherein, at a circumferential edge portion of the base member on its side where the rear surface is located, a protrusion portion which protrudes in a thickness direction is disposed.

A package structure and method of forming the same are provided. The package structure includes a die, a first dielectric layer, a second dielectric layer and a conductive terminal. The first dielectric layer covers a bottom surface of the die and includes a first edge portion and a first center portion in contact with the bottom surface of the die. The first edge portion is thicker than the first center portion. The second dielectric layer is disposed on the first dielectric layer and laterally surrounding the die. The second dielectric layer includes a second edge portion on the first edge portion and a second center portion in contact with a sidewall of the die. The second edge portion is thinner than the second center portion. The conductive terminal is disposed over the die and the second dielectric layer and electrically connected to the die.

Provided is a semiconductor package including: at least one first substrate including at least one first substrate terminal extended therefrom; at least one second substrate joined to the upper surface of the first substrate using ultrasonic welding; at least one semiconductor chip joined to the upper surface of the second substrate; a package housing covering the at least one semiconductor chip and an area of the second substrate, where ultrasonic welding is performed; and terminals separated from the first substrate, electrically connected to the at least one semiconductor chip through electric signals, and at least one of them is exposed to the outside of the package housing, wherein a thickness of the terminals formed inside the package housing is same as or smaller than a thickness of the first substrate and the second substrate includes at least one embossing groove on the upper surface thereof.

One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.

A lead frame wiring structure including first and second bonding parts positioned apart from each other, and a coupling part extending in a first direction to couple the first and second bonding parts. The coupling part includes a coupling face section, and first and second leg sections extending respectively from two opposite end portions of the coupling face section toward the first and second bonding parts. The first bonding part includes a wide section having a side edge portion and a peripheral section adjacent to the side edge portion in a second direction, and a narrow section protruding in the first direction from the side edge portion. In the coupling part, the coupling face section is spaced apart from the two bonding parts in a third direction, and the first leg section is connected to the peripheral section of the first bonding part. The first to third directions are perpendicular to one another.

An electronics assembly includes a semiconductor device having a first device surface and at least one device conductive layer disposed directly thereon. A cooling structure coupled to the semiconductor device includes a manifold layer, a microchannel layer bonded to the manifold layer, at least one planar side cooling structure, and one or more cooling structure conductive layers. The manifold layer includes a fluid inlet and a fluid outlet and defines a first cooling structure surface. The microchannel layer comprises at least one microchannel fluidly coupled to the fluid inlet and the fluid outlet and defines a second cooling structure surface opposite from the first cooling structure surface. The planar side cooling structure surface is transverse to the first and the second cooling structure surfaces. The cooling structure conductive layers are disposed directly on the first cooling structure surface, the second cooling structure surface, and the planar side cooling structure surface.

The present invention relates to a flexible thermoelectric module and, more specifically, to a flexible thermoelectric module used in the shape of a curved surface. A flexible thermoelectric module used in the shape of a curved surface according to the present invention includes a substrate provided in a plate shape transformable into the shape of a curved surface, a plurality of thermoelectric elements comprising an N-type semiconductor and a P-type semiconductor disposed so as to form a two-dimensional array on the substrate, and a plurality of electrodes connecting the N-type semiconductor and P-type semiconductor, wherein the plurality of thermoelectric elements form a thermoelectric line comprising thermoelectric elements consecutively connected by means of the electrodes and forming a line, wherein an extension direction of the thermoelectric line can be closer to a direction perpendicular to a curving direction for transformation into the shape of a curved surface than the curving direction.

A connection body, a method for manufacturing a connection body, and a connection method which can secure conduction reliability by trapping conductive particles even when the bump size is minimized. In a connection body in which a first component having a first electrode and a second component having a second electrode are connected to each other via a filler-containing film having a filler-aligned layer in which independent fillers are aligned in a binder resin layer, the maximum effective connection portion area where the first electrode and the second electrode face each other is 4,000 μm.sup.2 or less and a ratio of the effective connection portion area to a particle area on the connection portion projection plane is 3 or more.

A 3D semiconductor device including: a first level, where the first level includes a first layer and first transistors, and where the first level includes a second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, where the third layer includes crystalline silicon; and where the second level includes at least one SerDes circuit.

A method of fabricating a semiconductor package may include forming a lower re-distribution layer, forming a stack, bonding the stack to a portion of the lower re-distribution layer, stacking a semiconductor chip on a top surface of the lower re-distribution layer, and forming an upper re-distribution layer on the semiconductor chip and the stack.