H01L2224/32502

LIQUID METAL TIM WITH STIM-LIKE PERFORMANCE WITH NO BSM AND BGA COMPATIBLE

Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

Semiconductor device package and methods of packaging thereof
10297583 · 2019-05-21 · ·

An embodiment of the present invention describes a method for forming a doped region at a first major surface of a semiconductor substrate where the first doped region being part of a first semiconductor device. The method includes forming an opening from the first major surface into the semiconductor substrate and attaching a semiconductor die to the semiconductor substrate at the opening. The semiconductor die includes a second semiconductor device, which is a different type of semiconductor device than the first semiconductor device. The method further includes forming a chip isolation region on sidewalls of the opening and surrounding the second semiconductor device, and singulating the semiconductor substrate.

Method for wafer bonding and compound semiconductor wafer

A method for wafer bonding includes: providing a semiconductor wafer having a first main face; fabricating at least one semiconductor device in the semiconductor wafer, wherein the semiconductor device is arranged at the first main face; generating trenches and a cavity in the semiconductor wafer such that the at least one semiconductor device is connected to the rest of the semiconductor wafer by no more than at least one connecting pillar; arranging the semiconductor wafer on a carrier wafer such that the first main face faces the carrier wafer; attaching the at least one semiconductor device to the carrier wafer; and removing the at least one semiconductor device from the semiconductor wafer by breaking the at least one connecting pillar.

Apparatus for eutectic bonding

An apparatus for eutectic bonding includes (a) a bonding frame that includes two substrates and (b) a frame device situated on the substrates, the frame device including two frames, the apparatus being usable to develop a eutectic, formed during bonding, in a spatially defined manner, whereby a volume formed by the frames and the substrates can be filled up completely with the eutectic.

Substrate composite, method and device for bonding of substrates
09682539 · 2017-06-20 ·

A method for bonding a first substrate to a second substrate including the steps of: making contact of a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, as a result of which a common contact area is formed; and producing a bond interconnection between the first substrate and the second substrate outside the common contact area. The invention also relates to a corresponding device and a substrate composite of a first substrate and a second substrate, in which a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, forms a common contact area, outside the common contact area there being a bond interconnection between the first substrate and the second substrate.

High-power electronic device packages and methods

A high power electronic device package constructed to include a high power electronic device having an epitaxial surface attached to a thermally conductive submount by a thermally conductive interface layer having a eutectic metal contact therein. A gallium nitride high electron mobility transistor (GaN HEMT) having a transistor structure formed of a GaN thin film layer bonded to a thermally conductive host substrate via a thermally conductive interface layer disposed therebetween, and a method of forming the GaN HEMT. The GaN HEMTs can be used in such applications as, for example, power amplifiers with x-band radio frequency (RF) power outputs for micro-radar applications.

Semiconductor device including an embedded surface mount device and method of forming the same

Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first side of a substrate, an active surface of a die bonded to the first side of the substrate by a first connector, and a surface mount device mounted to the die by a second set of connectors, the surface mount device being between the die and the first side of the substrate, the surface mount device being spaced from the solder resist coating.

Semiconductor package structure and method for manufacturing the same

The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.

Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant

A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Solid metal foam thermal interface material
12300567 · 2025-05-13 · ·

Solid metal foam thermal interface materials and their uses in electronics assembly are described. In one implementation, a method includes: applying a thermal interface material (TIM) between a first device and a second device to form an assembly having a first surface of the TIM in in touching relation with a surface of the first device, and a second surface of the TIM opposite the first surface in touching relation with a surface of the second device, the TIM comprising a solid metal foam and a first liquid metal; and compressing the assembly to form an alloy from the TIM that bonds the first device to the second device.