The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.

An encoding method, decoding method, encoding device and decoding device for structured LDPC codes. The method includes: determining a basic matrix used for encoding, which includes K0 up-and-down adjacent pairs; and according to the basic matrix and an expansion factor corresponding to the basic matrix, performing an LDPC encoding operation of obtaining a codeword of Nb×z bits according to source data of (Nb−Mb)×z bits, herein z is the expansion factor, and z is a positive integer which is greater than or equal to 1. The provided technical solution is applicable to the encoding and decoding of the structured LDPC, thereby realizing the encoding and decoding of LDPC at the high pipeline speed.

.[.A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[H.sub.d|H.sub.p], H.sub.d is the data portion, and H.sub.p is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing..]. .Iadd.System and method for operating a wireless device to encode data using low-density parity-check (LDPC) encoding is discussed. One example method includes: computing a number of modulated orthogonal frequency-division multiplexing (OFDM) symbols for transmitting the data; computing a number of shortening bits; distributing the number of shortening bits over the at least one LDPC codeword; computing a number of puncturing bits for the at least one LDPC codeword; distributing the number of puncturing bits over the at least one LDPC codeword; determining a criterion using at least one of the number of shortening bits and the number of puncturing bits; if the criterion is met, increasing the number of modulated OFDM symbols and recalculating the number of puncturing bits; generating the encoded data using the number of shortening bits, the number of puncturing bits, and the at least one LDPC codeword; and transmitting the encoded data..Iaddend.

The disclosure discloses a method for supporting low bit rate coding. A source data packet to be coded is repeated for i times, and the data packet which is repeated for i times is coded. The disclosure also discloses an apparatus for supporting low bit rate coding and a computer storage medium.

The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.

Disclosed relates to a decoder for LDPC code, including: a variable node processing unit; a check node processing unit; a memory for storing iterative messages of edges of a parity-check matrix for LDPC code; and a controller for controlling the node processing units to perform iterations of decoding until the decoding ends, wherein, in each iteration of decoding, the controller controls the variable node processing unit to compute variable node messages in a traversing manner for all variable nodes and updates the iterative messages in the memory according to the computed variable node messages, and controls the check node processing unit to compute check node messages in a traversing manner for all check nodes and updates the iterative messages in the memory according to the computed check node messages.

Methods and devices are disclosed for receiving and detecting sparse data sequences using a message passing algorithm (MPA) with early propagation of belief messages. Such data sequences may be used in wireless communications systems supporting multiple access, such as sparse code multiple access (SCMA) systems. The determination and passing of one or more messages for an edge between a function node and a variable node in a factor graph representation of the system may be performed in serial with determined values available early for subsequent computations. The serial computations may be scheduled based on various factors.

Apparatuses, systems, and techniques to decode encoded data for fifth-generation (5G) new radio (NR). In at least one embodiment, a processor includes one or more circuits to select one or more data decoding operations to decode one or more 5G signals based, at least in part, on a sparsity of data received by the processor.

A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.

A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.