A wafer bonding technique to fabricate GaN devices is disclosed. In this technique, a GaN layer (or a GaN stack including at least one GaN layer) is fabricated on a first substrate (e.g., a silicon substrate) and has a high quality surface with a dislocation density less than 10.sup.10/cm.sup.2. The assembly of the first substrate and the GaN layer is then bonded to a second substrate (e.g., a carbide substrate or an AlN substrate) by coupling the high quality surface to the second substrate. The high quality of the GaN surface in contact with the carbide substrate creates a good thermal contact. The first substrate is etched away to expose a GaN surface for further processing, such as electrode formation.

A lateral bipolar junction transistor (LBJT) device that includes an intrinsic III-V semiconductor material having a first band gap; and a base region present on the intrinsic III-V semiconductor material. The base region is composed of an III-V semiconductor material having a second band gap that is less than the first band gap. Emitter and collector regions present on opposing sides of the base region. The emitter and collector regions are composed of epitaxial III-V semiconductor material that is present on the intrinsic III-V semiconductor material.

A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (θ1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.

A surface treatment method for a semiconductor layer includes growing a first layer on a substrate in a growth reactor, the first layer consisting of one of gallium nitride, aluminum gallium nitride and indium aluminium nitride; growing a second layer of gallium nitride on a surface of the first layer, the gallium nitride of the second GaN layer having a composition ratio of gallium to nitrogen larger than 2; taking the substrate out of the growth reactor after growing the second layer; and removing the second layer after taking the substrate out of the growth reactor.

A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) bottom n-type ohmic contact layer, ii) p-type modulation doped quantum well structure (MDQWS) with a p-type charge sheet formed above the bottom n-type ohmic contact layer, iii) n-type MDQWS offset vertically above the p-type MDQWS, and iv) etch stop layer formed above the p-type MDQWS. P-type ions are implanted to define source/drain ion-implanted contact regions of a p-channel HFET which encompass the p-type MDQWS. An etch operation removes layers above the etch stop layer of iv) for the source/drain ion-implanted contact regions using an etchant that automatically stops at the etch stop layer of iv). Another etch operation removes remaining portions of the etch stop layer of iv) to form mesas that define an interface to the source/drain ion-implanted contact regions of the p-channel HFET. Source/Drain electrodes are on such mesas.

In a substrate processing method according to the embodiment, a first material is implanted into a surface of a target film to modify the surface of the target film. The surface of the target film is dissolved to remove the surface of the target film by bringing a catalytic material close to the surface of the target film or by contacting the catalytic material to the surface of the target film while supplying a process solution on the surface of the target film which has been modified.

Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.

A method of metal-assisted chemical etching comprises forming an array of discrete metal features on a surface of a semiconductor structure, where each discrete metal feature comprises a porous metal body with a plurality of pores extending therethrough and terminating at the surface of the semiconductor structure. The semiconductor structure is exposed to an etchant, and the discrete metal features sink into the semiconductor structure as metal-covered surface regions are etched. Simultaneously, uncovered surface regions are extruded through the pores to form anchoring structures for the discrete metal features. The anchoring structures inhibit detouring or delamination of the discrete metal features during etching. During continued exposure to the etchant, the anchoring structures are gradually removed, leaving an array of holes in the semiconductor structure.

A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.

Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.