A method for manufacturing a semiconductor structure includes: a substrate is provided; the substrate is etched to form a blind hole, a sidewall of the blind hole has a first roughness; at least one planarization process is performed on the sidewall of the blind hole until the sidewall of the blind hole has a preset roughness less than the first roughness. The planarization process includes: a first sacrificial layer is formed on the sidewall of the blind hole; a reaction source gas is provided such that the reaction source gas reacts with the first sacrificial layer and a portion of the substrate at the sidewall of the blind hole to form a second sacrificial layer; and the second sacrificial layer is removed, and after the second sacrificial layer is removed, the sidewall of the blind hole has a second roughness less than the first roughness.

A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.

Disclosed is a field-effect transistor and a method for manufacturing a field-effect transistor. The method comprises: forming an NMOSFET region and a PMOSFET region on a substrate; forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region; forming a first array of nanowires in the NMOSFET region and a second array of nanowires in the PMOSFET region; and forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array. Wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation.

A method for manufacturing a semiconductor device according to an embodiment is a method for manufacturing a semiconductor device including performing a first etching process of forming a recess in a layer to be processed formed on a substrate by reactive ion etching using a first gas, performing a first process of supplying hydrogen radicals to the recess by using a second gas containing hydrogen in a state where a temperature of the substrate is equal to or more than 200° C. and equal to or less than 350° C. after the first etching process, and performing a second etching process of etching a bottom surface of the recess by reactive ion etching using a third gas after the first process.

A structure is manufactured by forming a mask that has an opening pattern on a fine recessed and projected structure of a substrate having the fine recessed and projected structure with an average period of 1 μm or less on a surface thereof, etching the surface of the substrate from a side of the mask to form a recessed portion which has an opening greater than the average period of the fine recessed and projected structure according to the opening pattern of the mask, the recessed portion having a depth equal to or greater than double a difference in height between recesses and projections of the fine recessed and projected structure, and then removing the mask.

An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer and having a plurality of element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and an individualization step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step including a step of irradiating a first laser beam, to form a first groove exposing the semiconductor layer in the dicing region, and a step of irradiating a second laser beam, with a beam center positioned outside a side wall of the first groove, to widen the first groove into the aperture.

An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer, the substrate having element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and a step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step includes a step of irradiating a first laser beam having a first pulse width, to remove the wiring layer in an edge portion of the dicing region, and a step of irradiating a second laser beam having a second pulse width which is longer than the first pulse width, to remove the wiring layer inside from the edge portion.

A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.

A method for etching silicon at cryogenic temperatures is provided. The method includes forming an inert layer from condensation of a noble gas at cryogenic temperatures on exposed surfaces such as the sidewalls of a feature to passivate the sidewalls prior to the etching process. The method further includes flowing a fluorine-containing precursor gas into the chamber to form a fluorine-containing layer on the inert layer. The method further includes exposing the fluorine-containing layer and the inert layer to an energy source to form a passivation layer on the exposed portions of the substrate and exposing the substrate to ions to etch the substrate.