In a SiC power MISFET having a lateral surface of a trench formed in an upper surface of a SiC epitaxial substrate as a channel region, a silicon carbide semiconductor device having low resistance, high performance, and high reliability is realized. As a means therefor, a SiC power MISFET is formed as an island-shaped unit cell on an upper surface of an n-type SiC epitaxial substrate that is provided with a drain region on a bottom surface thereof, the SiC power MISFET including: an n-type current diffusion region that surrounds a p-type body layer contact region and an n-type source region in the indicated order in a plan view; a p-type body layer and an n-type JFET region; a trench that is formed on the body layer so as to span between the source region and the current diffusion region adjacent each other in a first direction and extends in the first direction; and a gate electrode embedded in the trench with a gate insulating film therebetween.

A method includes forming a first-type deep well with a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first-type deep well to form a second-type doped region, in which a concentration of the first impurity in the first-type deep well is greater than a concentration of the second impurity in the second-type doped region and less than about ten times the concentration of the second impurity in the second-type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide laterally extending from a first side of the second-type doped region; forming a second-type well of the second conductivity type in the first-type deep well and on a second side of the second-type doped region opposite the first side of the second-type doped region.

A silicon carbide semiconductor device includes an ohmic electrode and a Schottky electrode that are in contact with the drain electrode respectively on the drain electrode and are next to each other; a first conductivity type first withstand voltage holding region in contact with the ohmic electrode on the ohmic electrode; a second conductivity type second withstand voltage holding region in contact with the Schottky electrode on the Schottky electrode and is next to the first withstand voltage holding region; a second conductivity type well region in contact onto the first and second withstand voltage holding regions; a first conductivity type source region selectively provided on a surface layer of the well region; and a gate electrode opposite to a channel region defined by the well region sandwiched between the source region and the first withstand voltage holding region, with a gate oxide film interposed therebetween.

An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Integrated circuits including LDMOS transistor structures and methods for fabricating LDMOS transistor structures are provided. An exemplary method for fabricating an LDMOS transistor structure includes providing a semiconductor-on-insulator (SOI) substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer. The method includes forming a gate structure overlying the substrate. A channel region is formed in the semiconductor layer under the gate structure. The method includes forming a source region overlying the substrate. Further, the method includes forming a drain region overlying the substrate. A drift region is located between the drain region and the gate structure. Also, the method includes forming contacts to the gate structure, the source region, and the drain region.

A semiconductor device includes a semiconductor substrate and a first well region formed in the semiconductor substrate. An insulator is formed in and over a portion of the first well region and a second well region is formed in the first well region at a first side of the insulator. A first doped region is formed in the second well region, and a second doped region is formed in the first well region at a second side opposite the first side of the insulator. A gate structure is formed over the insulator, the first well region between the second well region and the insulator, and the second well region. An isolation element is formed in the semiconductor substrate, surrounding the first well region and the second well region. The first and second doped regions are formed with asymmetric configurations from a top view.

A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.

A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in contact with the main surface of the silicon carbide layer. The silicon carbide layer includes a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and being in contact with the drift region, a source region having the first conductivity type and arranged as being spaced apart from the drift region by the body region, and a protruding region arranged to protrude from at least one side of the source region and the drift region into the body region, being in contact with the gate insulating layer, and having the first conductivity type.

A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.