An integrated circuit (IC) structure includes a first cell and a second cell abutting the first cell. The first cell includes a first fin-like field-effect transistor (FinFET). The first FinFET includes a first channel region in a first fin extending along a first direction, and a first gate electrode extending across the first channel region in the first fin along a second direction different from the first direction. The second FinFET includes a second channel region in a second fin aligned with the first fin along the first direction, and a second gate electrode extending across the second channel region in the second fin along the second direction. The second fin has a smaller width than the first fin.

A semiconductor device includes an inversion type semiconductor element including: a semiconductor substrate; a first conductive type layer formed on the semiconductor substrate; an electric field blocking layer formed on the first conductive type layer and including a linear shaped portion; a JFET portion formed on the first conductive type layer and having a linear shaped portion; a current dispersion layer formed on the electric field blocking layer and the JFET portion; a deep layer formed on the electric field blocking layer and the JFET portion; a base region formed on the current dispersion layer and the deep layer; a source region formed on the base region; trench gate structures including a gate trench, a gate insulation film, and a gate electrode, and arranged in a stripe shape; an interlayer insulation; a source electrode; and a drain electrode formed on a back surface side of the semiconductor substrate.

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

Disclosed is a semiconductor device and a manufacturing method, comprising: successively forming a pad oxide layer and a silicon nitride layer on a substrate; etching the silicon nitride layer into a plurality of segments; forming an oxide layer, having an up-and-down wavy shape, by performing a traditional thermal growth field oxygen method on the obtained semiconductor device by use of the plurality of segments serving as forming-assisted structures; performing traditional processes on the obtained semiconductor device having an up-and-down wavy semiconductor surface, to form a gate oxide layer, a polysilicon layer, and to form a source region and a drain region by implantation, thus the semiconductor device comprises a channel region with an up-and-down wavy shaped can be manufactured. According to the present disclosure, a semiconductor device having an up-and-down wavy channel region may be formed by use of a traditional thermal growth field oxygen method, the manufacturing processes are simple, the cost is low, and the completed device may have a larger effective channel width and a lower on-state resistance.

Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.

A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

A compound semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a JFET region of the first conductivity type disposed above the drift region, a body region of a second conductivity type disposed above the drift region and adjacent to the JFET region, and a JFET embedded region of the second conductivity type or i-type disposed in the JFET region. The JFET region has a bottom surface portion adjacent to the drift region, a side surface portion adjacent to the body region, and an inside portion adjacent to the JFET embedded region, and further has a high concentration portion at the bottom surface portion and the side surface portion. The high concentration portion has an impurity concentration higher than an impurity concentration of the inside portion.

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is located on the first electrode. The first semiconductor region includes a first region. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction. The third semiconductor region is located between the first and second semiconductor regions. A length in the second direction of a lower portion of the third semiconductor region is greater than a length in the second direction of an upper portion of the third semiconductor region. The fourth semiconductor region is located between the third semiconductor region and the gate electrode. The fifth semiconductor region is located on the second semiconductor region.

A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.