Disclosed herein are methods for backside wafer dopant activation using a high-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a high-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.

A semiconductor device has a cell part and a terminal part set in the device. The terminal part encloses the cell part. The semiconductor device includes a first electrode, a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, and an insulating layer. The first semiconductor layer is formed above the first electrode. The second semiconductor layer is provided in an upper portion of the first semiconductor layer, and has an impurity concentration profile along a vertical direction including a plurality of peaks. The insulating layer is provided on the second semiconductor layer.

A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.

An RC IGBT includes: an active region with separate IGBT and diode sections; a semiconductor body forming a part of the active region; a first load terminal and control terminal at a first side of the body and a second load terminal at a second side, the control terminal including a control terminal finger that laterally overlaps, in the active region, with the diode section. Control trenches extending into the semiconductor body along a vertical direction have a control trench electrode electrically connected to the control terminal for controlling a load current between the load terminals in the IGBT section. At least one control trench extends into both IGBT and diode sections. The electrical connection between the control trench electrode of that control trench and the control terminal is established at least based on an electrically conductive member arranged, in the diode section, in contact with the control terminal finger.

A thin non-punch-through semiconductor device with a patterned collector layer on the collector side is proposed. The thin NPT RC-IGBT semiconductor device has a collector layer with a pattern of p/n shorts, an emitter side structured as a functional MOS cell, a base layer arranged between the emitter and the collector sides, but without the use of a buffer/field-stop layer. A low doped bipolar gain control layer having a thickness of less than 10 μm may be used in combination with a short pattern of the collector to reduce the bipolar gain and achieve thinner devices with lower losses and high operating temperature capability. The doping concentration of the base layer and a thickness of the base layer are adapted such that the distance from the end of the electric field region to the patterned collector, at breakdown voltage, is less than 15% of the total device thickness.

A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.

A Metal Oxide Semiconductor (MOS) transistor cell design has multiple trench recesses embedding trench gate electrodes longitudinally extending in a third dimension, with interconnected first base layer, source regions, and a second base layer covering portions of the regions between adjacent trench recesses and longitudinally extending in the same third dimension. When a control voltage greater than a threshold value is applied on the trench gate electrodes, no vertical MOS channels are formable on the trench walls because each of trench recesses abuts at least one source regions and a connected highly doped second base layer. Instead, the charge carriers flow from a singular point within the source region, into a radial MOS channel formed only on the lateral walls of those trench regions abutting the first base layer, but not the higher doped second base layer.

A semiconductor device is proposed. The semiconductor device includes a semiconductor substrate including a RC-IGBT with a diode area. The diode area includes a p-doped anode region and an n-doped emitter efficiency adjustment region. At least one of the p-doped anode region or the n-doped emitter efficiency adjustment region includes deep level dopants.

Provided is a manufacturing method of a semiconductor device comprising a semiconductor substrate which includes a first surface and a second surface which is on an opposite side of the first surface, the method comprising: a front surface processing for providing a first resist to the first surface of the semiconductor substrate and processing the first surface; a first protective film forming for forming a first protective film above the first surface of the semiconductor substrate; a second protective film forming for forming a second protective film above the first protective film, wherein a material of the second protective film is different from that of the first protective film; a back surface processing for processing the second surface of the semiconductor substrate; and a protective film removing for selectively removing the second protective film.