Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

An FDSOI device structure and its fabrication method are disclosed. The device includes a silicon substrate; a buried oxide layer on the silicon substrate; a SiGe channel on the buried oxide layer, wherein the SiGe channel has a thickness in a range of 60-100 Å; a silicon layer on the SiGe channel layer; a metal gate disposed on the silicon layer, and sidewalls attached to both sides of the metal gate; and source-drain regions disposed on the silicon layer at both sides of the metal gate, wherein the source-drain regions are built in raised SiGe layers. The invention discloses a channel forming method for the FDSOI device, the method includes making a SiGe layer and an epitaxially grown silicon layer. This channel has avoided issues such as the low stress of a silicon channel and the Ge diffusion into the gate dielectric as occurred in the conventional process, thereby improving the reliability and performance of the FDSOI device.

An FDSOI device structure and its fabrication method are disclosed. The device includes a silicon substrate; a buried oxide layer on the silicon substrate; a SiGe channel on the buried oxide layer, wherein the SiGe channel has a thickness in a range of 60-100 Å; a silicon layer on the SiGe channel layer; a metal gate disposed on the silicon layer, and sidewalls attached to both sides of the metal gate; and source-drain regions disposed on the silicon layer at both sides of the metal gate, wherein the source-drain regions are built in raised SiGe layers. The invention discloses a channel forming method for the FDSOI device, the method includes making a SiGe layer and an epitaxially grown silicon layer. This channel has avoided issues such as the low stress of a silicon channel and the Ge diffusion into the gate dielectric as occurred in the conventional process, thereby improving the reliability and performance of the FDSOI device.

A semiconductor device structure comprises a region of semiconductor material comprising a first conductivity type, a first major surface, and a second major surface opposite to the first major surface. A first trench gate structure includes a first trench extending from the first major surface into the region of semiconductor material, a first dielectric structure is over sidewall surfaces and a portion of a lower surface of the first trench, wherein the first dielectric structure comprises a first opening adjacent to the lower surface of the first trench, a first recessed contact extends through the first opening, and a first contact region is over the first recessed contact within the first trench, wherein the first recessed contact and the first contact region comprise different materials. A first doped region comprising a second dopant conductivity type opposite to the first conductivity type is in the region of semiconductor material and is spaced apart from the first major surface and below the first trench. A gate contact region is in the region of semiconductor material and is electrically connected to the first doped region.

The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.

An ion implanted region is formed by implanting Mg ions into a predetermined region of the surface of the first p-type layer. Subsequently, a second n-type layer is formed on the first p-type layer and the ion implanted region. A trench is formed by dry etching a predetermined region of the surface of the second n-type layer until reaching the first n-type layer. Next, heat treatment is performed to diffuse Mg. Thus, a p-type impurity region is formed in a region with a predetermined depth from the surface of the first n-type layer below the ion implanted region. Since the trench is formed before the heat treatment, Mg is not diffused laterally beyond the trench. Therefore, the width of the p-type impurity region is almost the same as the width of the first p-type layer divided by the trench.

A method for fabricating a field-effect transistor includes: providing a structure including a first layer of semiconductor material, a doped second layer of semiconductor material arranged on top of the first layer of semiconductor material, the composition of which is different from that of the first layer, two spacers made of dielectric material arranged on top of the second layer of semiconductor material and separated by a groove, the second layer of semiconductor material being accessible at the bottom of the groove; etching the second layer of semiconductor material at the bottom of the groove until reaching the first layer of semiconductor material in such a way as to retain the second layer of semiconductor material beneath the spacers on either side of the groove; and then forming a gate stack in the groove.

Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.

The present invention provides an image pickup device that recognizes the object that the user is attempting to capture as the subject, tracks the movement of that subject, and can continue tracking the movement of the subject even when the subject leaves the capturing area so that the subject can always be reliably brought into focus. The image pickup device includes a main camera that captures the subject; an EVF that displays the captured image captured by the main camera, a sub-camera that captures the subject using a wider capturing region than the main camera, and a processing unit that extracts the subject from the captured images captured by the main camera and the sub-camera, tracks the extracted subject, and brings the subject into focus when an image of the subject is actually captured. When the subject moves outside of a capturing region of the main camera, the processing unit tracks the subject extracted from the captured image captured by the sub-camera.