A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

A semiconductor device having an IE-type IGBT structure comprises a stripe-shaped trench gate and a stripe-shaped trench emitter arranged to face the trench gate formed in a semiconductor substrate. The semiconductor device further comprises an N-type emitter layer and a P-type base layer both surrounded by the trench gate and the trench emitter formed in the semiconductor substrate. The semiconductor device also comprises a P-type base contact layer arranged on one side of the trench emitter and formed in the semiconductor substrate. The p-type base contact layer, the emitter layer, and the trench emitter are commonly connected with an emitter electrode. The trench emitter is formed deeper than the trench gate in a thickness direction of the semiconductor substrate.

An IGBT chip having a mixed gate structure includes a plurality of mixed gate units. Each of the mixed gate units includes a source region (3) and a gate region. The gate region includes a planar gate region (1) and a trench gate region (2), which are respectively disposed at both sides of the source region (3). A planar gate and a trench gate are compositely disposed on the same cell (16), thereby greatly improving chip density while retaining both trench gate's features of low on-state energy loss and high current density and planar gate's feature of wide safe operating area.

A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.

A power semiconductor device includes: a semiconductor body; a control electrode at least partially on or inside the semiconductor body; elevated source regions in the semiconductor body adjacent to the control electrode; recessed body regions adjacent to the elevated source regions; and a dielectric layer arranged on a portion of a surface of the semiconductor body and defining a contact hole. The contact hole is at least partially filled with a conductive material establishing an electrical contact with at least a portion of the elevated source regions and at least a portion of the recessed body regions. At least one first contact surface between at least one elevated source region and the dielectric layer extends in a first horizontal plane. At least one second contact surface between at least one recessed body region and the dielectric layer extends in a second horizontal plane located vertically below the first horizontal plane.

A power semiconductor device includes a control cell for controlling a load current. The control cell is electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including: a contact region having dopants of the first conductivity type or of a second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to induce a conduction channel in the channel region; and a contact plug including a doped semiconductive material and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which projects beyond lateral boundaries of the mesa.

A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer in which a device formation region and an outer region outside the device formation region are set, a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region, an emitter region of a first conductivity type formed in a surface layer portion of the channel region, a gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region, an inner cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the device formation region, and an outer cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the outer region.

A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body, the trench structure having a gate electrode that is dielectrically insulated from the semiconductor body, a shielding region adjoining a bottom of the trench structure and forming a first pn junction with a drift structure of the semiconductor body, a body region forming a second pn junction with the drift structure, a source zone arranged between the first surface and the body region and forming a third pn junction with the source zone, wherein a contact portion of the body region extends to the first surface, wherein the source zone surrounds the contact portion of the body region at the first surface, and wherein the trench structure forms an enclosed loop at the first surface that surrounds the source zone and the contact portion of the body region at the first surface.