Disclosed is a semiconductor device, an electronic circuit, and a method. The semiconductor device includes a semiconductor body; at least one transistor cell including a source region, a drift region, a body region separating the source region from the drift region, and a drain region in the semiconductor body, and a gate electrode dielectrically insulated from the body region by a gate dielectric; a source node connected to the source region and the body region; a contact node spaced apart from the body region and the drain region and electrically connected to the drain region; and a rectifier element formed between the contact node and the source node.

In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.

In a general aspect, a field-effect transistor (FET) can include a semiconductor region, and a trench disposed in the semiconductor region. The FET can also include a trench gate disposed in an upper portion of the trench in an active region of the FET. The FET can further include a conductive runner disposed in a bottom portion of the trench. The conductive runner can be electrically coupled with a drain terminal of the FET. A portion of the conductive runner can be disposed in the active region below the trench gate.

A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

A method of manufacturing a super junction structure includes etching a material to define a trench, wherein the trench has a tapered profile. The method further includes implanting dopants into sidewalls and a bottom surface of the trench to define a doped region, wherein the doped region surrounds the trench. The method further includes depositing an undoped material into the trench. The method further includes performing a thermal process, wherein the thermal process drives the dopants from the doped region into the undoped material to form a conductive pillar in the trench.

A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.

Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode. The one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device.

A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.

A nano-wall integrated circuit structure with high integration density is disclosed, which relates to the fields of microelectronic technology and integrated circuits (IC). Based on the different device physical principles with MOSFETs in traditional ICs, the nano-wall integrated circuit unit structure (Nano-Wall FET, referred to as NWaFET) with high integration density can improve the integration of the IC, significantly shorten the channel length, improve the flexibility of the device channel width-to-length ratio adjustment, and save chip area.