A FinFET whose fin has an upper portion doped with a first conductivity type and a lower portion doped with a second conductivity type, and the junction between the upper portion and the lower portion acts as a diode. The FinFET further includes: at least one layer of high-k dielectric material (for example Si.sub.3N.sub.4) adjacent at least one side of the fin for redistributing a potential drop more evenly over the diode. Examples of the k value for the high-k dielectric material are k≧5, k≧7.5, and k≧20.

A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming an isolation structure surrounding the fin structure. The method also includes cleaning sidewalls of the fin structure. The method also includes depositing a silicon cap layer over the fin structure. The method also includes growing an oxide layer over the silicon cap layer. The silicon cap layer is thinned after growing an oxide layer over the silicon cap layer. The method also includes forming a gate structure over the oxide layer across the fin structure. The method also includes growing a source/drain epitaxial structure beside the gate structure. The method also includes forming a contact structure electrically connected to the gate structure.

A method includes forming a first portion of a spacer layer over a first fin and a second portion of the spacer layer over a second fin, performing a first etching process to recess the first portion of the spacer layer with respect to the second portion of the spacer layer to form first spacers on sidewalls of the first fin, subsequently performing a second etching process to recess the second portion of the spacer layer with respect to the first spacers to form second spacers on sidewalls of the second fin, where the second spacers are formed to a height greater than that of the first spacers, and forming a first epitaxial source/drain feature and a second epitaxial source/drain feature between the first spacers and the second spacers, respectively, where the first epitaxial source/drain feature is larger than that of the second epitaxial source/drain feature.

The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

The embodiments of the present disclosure provide a memory and a manufacturing method of a memory. The memory includes first fins and second fins disposed on a substrate, a dielectric layer covering tops of the first fins and side wall surfaces exposed by an isolating structure, and work function layers disposed on a surface of the dielectric layer. In a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on the side walls where the adjacent first fins are opposite are provided with a first thickness, and the work function layers on the side walls where the first fins face towards the second fins are provided with a second thickness. The first thickness is greater than the second thickness.

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.

A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other. In addition, the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers. The semiconductor structure further includes first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively. In addition, the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features.

A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region. First and second dielectric films are positioned above the substrate in the first region and the second region, respectively. First and second gate stacks are disposed on the first and second dielectric films, respectively. The first gate stack includes a first TiAlC film in direct contact with the first dielectric film, and a first barrier film and a first metal film sequentially stacked on the first TiAlC film. The second gate stack includes a first LaO film in direct contact with the second dielectric film. A second TiAlC film, a second barrier film, and a second metal film are sequentially stacked on the first LaO film.