H01L29/78618

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The semiconductor device structure includes an isolation structure over the base and surrounding a lower portion of the fin structure. The semiconductor device structure includes a gate stack wrapped around an upper portion of the fin structure. The semiconductor device structure includes a source/drain structure partially embedded in the isolation structure and the lower portion of the fin structure. The source/drain structure has an undoped semiconductor layer and a first doped layer over the undoped semiconductor layer, and the undoped semiconductor layer separates the first doped layer from the isolation structure.

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME USING HARD MASK

A semiconductor device includes an underlying substrate, two stack units disposed over the underlying substrate, and a feature disposed between the stack units. The stack units are spaced apart from each other. Each of the stack units includes a plurality of conductive films and a plurality of dielectric films disposed to alternate with the conductive films, an inter-metal dielectric (IMD) portion, and a hard mask film. An uppermost one of the dielectric films of each of the stack units is disposed over the conductive films, and has a dimension smaller than those of the conductive films and those of remaining ones of the dielectric films of each of the stack units. The feature includes a plurality of repeating units and a plurality of separators which are disposed to alternate with the repeating units. A method for manufacturing the semiconductor device is also disclosed.

Semiconductor device and method for manufacturing the same

A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

Silicide-sandwiched source/drain region and method of fabricating same

A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL
20230019866 · 2023-01-19 ·

A semiconductor device, a manufacturing method thereof, and a display panel are provided. The semiconductor device includes a first active component. The first active component includes a first semiconductor layer and a contact layer. The contact layer includes a first doped layer, a second semiconductor layer, and a second doped layer stacked from bottom to top, so that there are at least two PN junction interfaces inside to increase a light to dark current ratio of the semiconductor device.

Semiconductor Devices Including Backside Capacitors and Methods of Manufacture

Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

Inner Spacer Features For Multi-Gate Transistors

A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a first active fin and a second active fin respectively extending in a first direction, the substrate having a recess between the first and second active fins, a device isolation film on the substrate, first and second gate structures on the first and second active fins, respectively, and extending in a second direction, and a field separation layer having a first portion between the first and second active fin and in the recess, and a second portion extending from both sides of the first portion in the second direction to an upper surface of the device isolation film. The recess has a bottom surface lower in a third direction intersecting the first direction and the second direction than the upper surface of the device isolation film, and a region of the upper surface of the device isolation film has a flat surface.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
20230019278 · 2023-01-19 ·

Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an active pattern on a substrate, a device isolation layer provided on the substrate to define the active pattern, a pair of source/drain patterns on the active pattern and a channel pattern therebetween, the channel pattern including semiconductor patterns which are stacked and are spaced apart from each other, a gate electrode crossing the channel pattern, and a gate spacer on a side surface of the gate electrode. The gate spacer located on the device isolation layer includes an upper portion with a first thickness and a lower portion with a second thickness. The second thickness is larger than the first thickness, and the lower portion of the gate spacer is located at a level lower than the uppermost one of the semiconductor patterns.

SEMICONDUCTOR DEVICES WITH A RARE EARTH METAL OXIDE LAYER

The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.