A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.

Provided are an array substrate, a display panel, a display apparatus and a method for manufacturing an array substrate. The array substrate includes: a base substrate; an active layer, which is located on one side of the base substrate, where the active layer includes a channel region, a conductive source region, which is located on one side of the channel region, and a conductive drain region, which is located on the other side of the channel region; and a metal layer, which is located on the side of the active layer that is away from the base substrate, where the metal layer includes a gate electrode and a signal line, which are arranged on the same layer, and the thickness of the gate electrode perpendicular to the base substrate is less than the thickness of the signal line perpendicular to the base substrate.

The present disclosure provides a display substrate, a manufacturing method, and a display device. The method includes: providing a base substrate; forming a driving circuitry layer on the base substrate; forming an inorganic insulation layer on the driving circuitry layer; forming a pattern of a planarization layer on the inorganic insulation layer, the planarization layer being made of an organic material; forming a first transparent conductive layer on the planarization layer; and forming a through hole through a patterning process, a photoresist used during the exposure of the patterning process including an organic material.

RF devices, and more particularly RF devices with photo-imageable polymers for high frequency enhancements and related methods are disclosed. High frequency enhancements are realized by providing air cavities registered with one or more operating portions of RF devices. The air cavities are formed by photo-imageable polymer structures that provide separation from high dielectric constant materials associated with sealing materials, such as overmold materials, that are typically used for environmental and/or mechanical protection in RF devices. Related methods are disclosed that include forming the photo-imageable polymer structures and corresponding air cavities through various lamination and patterning of photo-imageable polymer layers. Further radiation hardening steps are disclosed that may be applied to the photo-imageable polymer structures after air cavities are formed to promote improved structural integrity of the air cavities during subsequent fabrication steps and during operation of the RF devices.

An active matrix substrate has pixel regions, and includes a substrate, pixel TFTs disposed to respectively correspond to the pixel regions, and pixel electrodes electrically connected to the pixel TFTs. The pixel TFTs are each a top gate structure TFT that has an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode opposing the oxide semiconductor layer with the gate insulating layer therebetween. The gate insulating layer is formed of silicon oxide and includes a lower layer contacting the oxide semiconductor layer, and an upper layer on the lower layer. The lower layer H/N ratio of hydrogen atoms to nitrogen atoms in the lower layer is 1.5 to 5.0. The upper layer H/N ratio of hydrogen atoms to nitrogen atoms in the upper layer is 0.9 to 2.0. The lower layer H/N ratio is larger than the upper layer H/N ratio.

An imaging device connected to a neural network is provided. An imaging device having a neuron in a neural network includes a plurality of first pixels, a first circuit, a second circuit, and a third circuit. Each of the plurality of first pixels includes a photoelectric conversion element. The plurality of first pixels is electrically connected to the first circuit. The first circuit is electrically connected to the second circuit. The second circuit is electrically connected to the third circuit. Each of the plurality of first pixels generates an input signal of the neuron. The first circuit, the second circuit, and the third circuit function as the neuron. The third circuit includes an interface connected to the neural network.

According to one embodiment, a display device includes a gate line extending in a first direction, first and second source lines crossing the gate line and arranged in the first direction, a first light-shielding layer having first and second openings, and an oxide semiconductor layer crossing the gate line, and in the display device, the first opening and the second opening are arranged in a second direction crossing the first direction between the first source line and the second source line, the gate line is located between the first opening and the second opening, and the oxide semiconductor layer has a first overlapping portion overlapping the first opening.

Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, methods for depositing silicon nitride materials are provided and include heating a workpiece to a temperature of about 200° C. to about 250° C., exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition process, and depositing a nitrogen-rich silicon nitride layer on the workpiece. The deposition gas contains a silicon precursor, a nitrogen precursor, and a carrier gas. A molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas within the deposition gas is about 1:a range from about 4 to about 8:a range from about 20 to about 80, respectively.

A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.