A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.

Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.

A method and apparatus wherein the method comprises: providing at least one electrode within a semiconductor layer wherein the semiconductor layer is provided on a first side of a wafer; thinning the wafer to produce a thinned wafer; providing graphene on a second side of the thinned wafer; attaching the semiconductor layer to an electrical interface on the first side of the thinned wafer; and providing at least one electrical connection from the graphene to the electrical interface so as to form a transistor comprising the at least one electrode and the graphene.

A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate, each of the antenna unit regions including a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate includes a gate metal layer supported by the dielectric substrate and including a gate electrode of the TFT, a source metal layer supported by the dielectric substrate and including a source electrode of the TFT, a semiconductor layer, supported by the dielectric substrate, of the TFT, a gate insulating layer formed between the gate metal layer and the semiconductor layer, and a flattened layer formed over the gate insulating layer and formed from an organic insulating material.

A manufacturing method of an array substrate, an array substrate and a display apparatus are provided. The manufacturing method includes: providing a base substrate; sequentially forming an active layer and a first insulating layer that covers the active layer on the base substrate; performing one patterning process on the first insulating layer, so as to form a first through hole and a second through hole that expose the active layer in the first insulating layer, and form a first recess at a surface of the first insulating layer; forming a conductive layer on the patterned first insulating layer, with the conductive layer being filled in the first through hole, the second through hole and the first recess; conducting a grinding process to form a source electrode, a drain electrode and a pixel electrode are formed respectively.

A thin film transistor substrate according to an embodiment comprises: a support substrate; a bonding layer disposed on the support substrate; a thin film transistor disposed on the bonding layer, wherein the thin film transistor includes a channel layer containing a nitride-based semiconductor layer, a source electrode electrically connected to a first region of the channel layer, a drain electrode electrically connected to a second region of the channel layer, a gate electrode disposed below the channel layer, and a depletion forming layer disposed between the channel layer and the gate electrode; and a pixel electrode disposed on the thin film transistor and electrically connected to the drain electrode of the thin film transistor. The thin film transistor substrate according to the embodiment, and a display panel and a display device including the same have an advantage of implementing high resolution and reproducing a soft moving image by providing a high carrier mobility.

A manufacturing method of the invention, comprising: successively forming an insulation layer and a photoresist layer on a transparent substrate; performing an exposure and a development on the photoresist layer by a back exposure process, so as to form a trench in the photoresist layer, an open area of the trench proximal to the insulation layer is larger than that of the trench distal to the insulation layer; removing a portion of insulation material in a region of the insulation layer exposed through the trench by an etching process, so as to form a slot in the insulation layer; forming a metal layer on a side of the photoresist layer distal to the insulation layer, a portion of the metal layer is embedded in the slot; removing the photoresist layer and the metal layer thereon by a stripping process, and retaining the portion of the metal layer in the slot.

A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.

The present application discloses a thin film transistor, a method for manufacturing a thin film transistor and a liquid crystal display panel, and relates to a display technology field. The thin film transistor includes a substrate, a gate electrode layer and an insulating layer, the gate electrode layer is formed on the substrate, the insulating layer is covered on the gate layer; a semiconductor layer is formed on the insulating layer; a conductor layer is formed on the semiconductor layer; an insulating spacer layer is formed on the insulating layer; a source-drain electrode layer is formed on the conductor layer and the insulating spacer layer; a passivation layer formed on the source-drain electrode layer and the semiconductor layer; wherein the insulating spacer layer is located between the source-drain electrode layer and the semiconductor layer to solve the leakage current too large problem of the thin film transistor.