A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.

A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.

Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include source and drain regions on opposing ends of the inverted T channel, and a gate overlying the inverted T channel between the source and drain regions.

A method for making a semiconductor device may include forming an inverted T channel on a substrate, with the inverted T channel comprising a superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source and drain regions on opposing ends of the inverted T channel, and forming a gate overlying the inverted T channel between the source and drain.

A semiconductor device includes a gate electrode, an insulating layer, a first carbon nanotube, a second carbon nanotube, a P-type semiconductor layer, an N-type semiconductor layer, a conductive film, a first electrode, a second electrode and a third electrode. The insulating layer is located on a surface of the gate electrode. The first carbon nanotube and the second carbon nanotube are located on a surface of the insulating layer. The P-type semiconductor layer and the N-type semiconductor layer are located on the surface of the insulating layer and apart from each other. The conductive film is located on surfaces of the P-type semiconductor layer and the N-type semiconductor layer. The first electrode is electrically connected with the first carbon nanotube. The second electrode is electrically connected with the second carbon nanotube. The third electrode is electrically connected with the conductive film.

In a first aspect of a present inventive subject matter, a layered structure includes a base layer, and a crystalline oxide film including a corundum structure and including an r-plane as a principal plane. The crystalline oxide film is directly arranged on the base layer or through at least one layer that is adjacently arranged to the base layer, and the crystalline oxide film is with a full width at half maximum (FWHM) of rocking curve that is 0.1 or less by -scan X-ray diffraction (XRD) measurement.