Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

The present application discloses a method for manufacturing a source/drain epitaxial layer of an FDSOI MOSFET, comprising: step 1, forming a shallow trench isolation on an FDSOI substrate; step 2, opening a formation region of a source/drain region of the MOSFET; step 3, performing first epitaxial growth to form a first pure silicon epitaxial layer; step 4, performing a first etching process to remove polysilicon particles generated from step 3; and step 5, performing epitaxial growth to sequentially form a second source/drain epitaxial seed layer, a third source/drain epitaxial bulk layer, and a fourth source/drain epitaxial cap layer on a surface of the first pure silicon epitaxial layer, so the four epitaxial layers are stacked to form the source/drain epitaxial layer.

Provided herein are devices, systems, and methods of employing the same for the performance of bioinformatics analysis. The apparatuses and methods of the disclosure are directed in part to large scale graphene FET sensors, arrays, and integrated circuits employing the same for analyte measurements. The present GFET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved GFET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense GFET sensor based arrays. Improved fabrication techniques employing graphene as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. Accordingly, GFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis within a gated reaction chamber of the GFET based sensor.

Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition.

A TFT structure based on a flexible multi-layer graphene quantum carbon substrate material and a method for manufacturing the same. The TFT structure includes a multi-layer graphene quantum carbon substrate, a first source, a first drain, a first gate insulating layer, and a first gate. The multi-layer graphene quantum carbon substrate includes a first channel area, and a first drain area and a first source area that are located at corresponding recessed positions on the multi-layer graphene quantum carbon substrate that are separated from each other. The first channel area is located between the first drain area and the first source area, the first source is filled in the first source area, the first drain is filled in the first drain area, the first gate insulating layer is disposed on the first channel area, and the first gate is disposed on the first gate insulating layer.

Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.

An electronic device includes a 2D material layer having a bandgap. The 2D material layer includes two multilayer 2D material regions and a channel region therebetween. A first electrode electrically contacts one of the multilayer 2D material regions, and a second electrode electrically contacts the other of the multilayer 2D material regions.

A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.

A semiconductor device includes a first electrode, a second electrode, a semiconductor element, an insulating layer and a third electrode. The semiconductor element is electrically connected to the first electrode and the second electrode. The third electrode is insulated from the semiconductor structure, the first electrode and the second electrode through the insulating layer. The semiconductor element includes a semiconductor structure, a carbon nanotube and a conductive film. The semiconductor structure includes a P-type semiconductor layer and an N-type semiconductor layer and defines a first surface and a second surface. The carbon nanotube is located on the first surface of the semiconductor. The conductive film is located on the second surface of the semiconductor. The conductive film is formed on the second surface by a depositing method or a coating method.