The present technology relates to an electronic substrate that achieves a reduction in the size of a substrate and enables a void risk in an underfill to be reduced, and an electronic apparatus. An electronic substrate in one aspect of the present technology includes: an electronic chip that is placed above a substrate; an electrode that exists between the substrate and the electronic chip and electrically connects the substrate and the electronic chip; an underfill with which a space between the substrate and the electronic chip is filled so that the electrode is sealed and protected; a protection target to be protected from inflow of the underfill, the protection target being formed on the substrate; and an underfill inflow prevention unit that is formed in the substrate so as to surround an entirety or a portion of the protection target. The present technology is applicable to, for example, a solid-state image sensor.

A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a plurality of conductive terminals. The first encapsulant is at least disposed between the first die and the second die, and on the second die. The second encapsulant is aside the first die and the second die. The conductive terminals are electrically connected to the first die and the second die through a redistribution layer (RDL) structure. An interface is existed between the first encapsulant and the second encapsulant.

A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

A package structure and a method of forming the same are provided. The package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure. The first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector. The first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other. The second encapsulant encapsulates second sidewalls of the first die and the second die. The RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.

A passive micro light-emitting diode matrix device with uniform luminance includes a micro light-emitting diode matrix including a plurality of micro light-emitting matrices, each of which includes a first layer, a plurality of light-emitting layers disposed on the first layer, a plurality of second layers disposed on the light-emitting layers, respectively, a plurality of first inner electrode layers disposed on the second layers, respectively, and a second inner electrode layer which is disposed on the first layer, and which includes a first portion and a second portion having a plurality of through holes to accommodate said light-emitting layers, respectively.

A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.

A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.