A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed.

A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.

A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

In an embodiment, a semiconductor device includes: a mounting substrate having electrically conductive formations thereon, a semiconductor die coupled with the mounting substrate, the semiconductor die with electrical contact pillars facing towards the mounting substrate, an anisotropic conductive membrane between the semiconductor die and the mounting substrate, the membrane compressed between the electrical contact pillars and the mounting substrate to provide electrical contact between the electrical contact pillars of the semiconductor die and the electrically conductive formations on the mounting substrate.

Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

A semiconductor device includes a semiconductor substrate, a front surface electrode provided on a front surface of the semiconductor substrate, a solder layer, and a metal member fixed to a front surface of the front surface electrode via the solder layer. The solder layer includes an inner solder portion positioned inner than an end portion of the metal member and an outer solder portion positioned outer than the end portion of the metal member, relative to a direction along the front surface of the semiconductor substrate. The semiconductor substrate includes an inner substrate portion positioned below the inner solder portion and an outer substrate portion positioned below the outer solder portion. A density of carriers that flow from the outer substrate portion to the front surface electrode is lower than a density of carriers that flow from the inner substrate portion to the front surface electrode.

A semiconductor device according to the present invention includes a semiconductor chip, a conductive member for supporting the semiconductor chip, a joint material provided between the conductive member and the semiconductor chip, and a release groove formed on the surface of the conductive member and arranged away from the semiconductor chip with the one end and the other end of the release groove connected to the peripheral edges of the conductive member, respectively.

A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.