The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

A semiconductor device includes: a first semiconductor element including a first face and a second face; a second semiconductor element including a third face and a fourth face; an insulating base member including a fifth face and a sixth face; a first wiring that penetrates through the insulating base member, and is disposed on the sixth face; a second wiring that penetrates through the insulating base member, and is disposed on the sixth face; a first wiring member that faces the second face; and a second wiring member that faces the sixth face, and is electrically connected to the second wiring. The second wiring member is bonded to the first and second wirings while the insulating base member is folded. A current flows in a first direction in the first wiring member, and flows in a second direction opposite to the first direction in the second wiring member.

The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

An underfill film material and a method for manufacturing a semiconductor device using the same which enables voidless mounting and favorable solder bonding properties are provided. An underfill material is used which contains an epoxy resin, an acid anhydride, an acrylic resin and an organic peroxide, the underfill material exhibits non-Bingham fluidity at a temperature ranging from 60° C. to 100° C., a storage modulus G′ measured by dynamic viscosity measurement has an inflection point in an angular frequency region below 10E+02 rad/s, and the storage modulus G′ in the angular frequency below the inflection point is 10E+05 Pa or more and 10E+06 Pa or less. This enables voidless packaging and excellent solder connection properties.

An underfill film material and a method for manufacturing a semiconductor device using the same which enables voidless mounting and favorable solder bonding properties are provided. An underfill material is used which contains an epoxy resin, an acid anhydride, an acrylic resin and an organic peroxide, the underfill material exhibits non-Bingham fluidity at a temperature ranging from 60° C. to 100° C., a storage modulus G′ measured by dynamic viscosity measurement has an inflection point in an angular frequency region below 10E+02 rad/s, and the storage modulus G′ in the angular frequency below the inflection point is 10E+05 Pa or more and 10E+06 Pa or less. This enables voidless packaging and excellent solder connection properties.

A piezoelectric vibration component that includes a piezoelectric vibrator, a substrate, and a conductive adhesive that bonds the piezoelectric vibrator to the substrate. The conductive adhesive contains a silicone-based base resin, a cross-linker, a conductive filler, and an insulating filler. The silicone-based base resin has a weight-average molecular weight of 20,000 to 102,000. The cross-linker has a number-average molecular weight of 1,950 to 4,620. The conductive filler and the insulating filler have a particle size of 10 μm or less.

A semiconductor package system is disclosed. The system includes a first interposer and a first integrated circuit die electrically coupled and thermally coupled to a first side of the first interposer. The system further includes a second integrated circuit die electrically coupled and thermally coupled to a second side of the first interposer. The system further includes a ring carrier electrically coupled and thermally coupled to the first interposer. The ring carrier is configured to transmit an input to the first interposer. In some embodiments, the system further includes at least one thermal spreader thermally coupled to the ring carrier and at least one of the first integrated circuit, the second integrated circuit, or the first interposer.

A semiconductor package system is disclosed. The system includes a first interposer and a first integrated circuit die electrically coupled and thermally coupled to a first side of the first interposer. The system further includes a second integrated circuit die electrically coupled and thermally coupled to a second side of the first interposer. The system further includes a ring carrier electrically coupled and thermally coupled to the first interposer. The ring carrier is configured to transmit an input to the first interposer. In some embodiments, the system further includes at least one thermal spreader thermally coupled to the ring carrier and at least one of the first integrated circuit, the second integrated circuit, or the first interposer.

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

A method for forming a package structure is provided. The method includes forming a first molding compound layer surrounding a first interposer. The method also includes forming a first redistribution structure over a first side of the first interposer and the first molding compound layer. The method also includes bonding a first semiconductor die and a second semiconductor die to the first redistribution structure through a plurality of first connectors. The method also includes bonding a surface-mount device (SMD) to the first redistribution structure through a second connector. The method also includes forming a second redistribution structure over a second side of the first interposer opposite the first side of the first interposer. A top surface of the surface-mount device (SMD) is lower than top surfaces of the first semiconductor die and the second semiconductor die.