A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Disclosed herein is a gas delivery assembly for processing a substrate. In one example, a processing chamber comprises a plurality of walls, a bottom, and a lid to form an interior volume. Gas nozzles provide gas into the interior volume. A substrate support is disposed in the interior volume, having a top surface that supports a substrate. A gas delivery assembly comprises a gas manifold, and is disposed outside of the processing chamber. Gas passageways extend from the gas manifold to the gas nozzles, each gas passageway having similar conductance. A controller is fluidically coupled to each of the gas passageways, and is configured to control the timing at which a first process gas flows from the gas delivery assembly through the controller into the gas manifold, and the timing at which a second process gas is injected into the gas manifold through the gas nozzles.

The inventive concept provides a substrate treating apparatus. In an embodiment the substrate treating apparatus includes a process chamber having a treating space therein for treating a substrate; a substrate support unit configured to support the substrate in the treating space; and a microwave application unit configured to apply a microwave to the treating space, and wherein the microwave application unit comprises a microwave power generator based on a solid state device.

A metal removal method which includes: a reaction step of bringing a treatment gas containing a fluorine-containing interhalogen compound and a metal-containing material containing a metal element into contact with each other to generate metal fluoride which is a reaction product of the fluorine-containing interhalogen compound and the metal element; and a volatilization step of heating the metal fluoride under an inert gas atmosphere or in a vacuum environment for volatilization. The metal element is at least one kind selected from iron, cobalt, nickel, selenium, molybdenum, rhodium, palladium, tungsten, rhenium, iridium, and platinum. Also disclosed is a dry etching method using the metal removal method and a production method for a semiconductor element using the dry etching method.

A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.

A method for manufacturing an III-nitride semiconductor structure is provided. The method includes providing a substrate comprising a first layer having an upper surface of monocrystalline III-nitride material; providing, over the upper surface, a patterned dielectric layer comprising a first dielectric feature; loading the substrate into a process chamber; exposing the substrate to a first gas mixture comprising at least one Group III-metal organic precursor gas, a nitrogen containing gas and hydrogen gas at a predetermined temperature, thereby forming, on the upper surface, a second layer of a monocrystalline III-nitride material by area selective growth wherein two opposing sidewalls of the dielectric feature are oriented parallel to one of the {11-20} crystal planes of the first layer such that upon formation of the second layer of the monocrystalline III-nitride material, a first trench having tapered sidewalls is formed so that the crystal plane of the second layer parallel to the tapered sidewalls is one of the {1-101} crystal planes.

A multilayer semiconductor structure of the present disclosure includes a substrate a buffer layer disposed on the substrate and a semiconductor layer disposed on the buffer layer. A void is provided between the buffer layer and the semiconductor layer.

A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.

A method for treating a substrate includes receiving the substrate in a vacuum process chamber. The substrate includes a III-V film layer disposed on the substrate. The III-V film layer includes an exposed surface, an interior portion underlying the exposed surface, and one or more of the following: Al, Ga, In, N, P, As, Sb, Si, or Ge. The method further includes altering the chemical composition of the exposed surface and a fraction of the interior portion of the III-V film layer to form an altered portion of the III-V film layer using a first plasma treatment, removing the altered portion of the III-V film layer using a second plasma treatment, and repeating the altering and removing of the III-V film layer until a predetermined amount of the III-V film layer is removed from the substrate.