Provided is a surface treatment method for a SiC substrate (40), the method being capable of controlling whether to generate a step bunching or the type of step bunching that is generated. In the surface treatment method in which the surface of the SiC substrate (40) is etched by heating the SiC substrate (40) under Si vapor pressure, an etching mode and an etching depth which are determined at least on the basis of an etching rate, are controlled to etch the SiC substrate (40), so that a surface pattern of the SiC substrate (40) after etching treatment is controlled.

A high electron mobility transistor (HEMT) made of nitride semiconductor materials, and a method to form the HEMT are disclosed. The HEMT includes a channel layer made of GaN, a barrier layer made of one of AlGaN, InAlN, and InAlGaN on the GaN channel layer, a cap layer made of n-type GaN on the barrier layer, and an insulating layer on the cap layer. The insulating layer has an opening into which the gate is formed. The cap layer has a region in the opening that has a thickness smaller than a thickness of portions of the cap layer that are outside of such region. The outside portions have a thickness that is preferably 5 nm at most.

A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

A method of fabricating a microelectronic device, such as a high electron mobility transistors (HEMT), is disclosed. In some examples, the method comprises placing a masked semiconductor sample into a treatment chamber. An oxidizing gas is introduced into the treatment chamber and ionized by an inductively-coupled plasma (ICP)-only plasma source to form a first plasma that oxidizes an exposed region of the sample surface. The oxidizing gas is then evacuated from the treatment chamber, and a reducing gas is introduced into the treatment chamber. The reducing gas in the treatment chamber is ionized via the ICP-only plasma source to form a second plasma that reduces the exposed region of the sample surface. The sample may be heated to a temperature of at least about 100° C. (e.g., 200° C.), resulting in the etching/removal of a portion of the exposed region of the sample via chemical conversion and thermal desorption.

An additive-containing aluminium nitride film is plasma etched. The additive-containing aluminium nitride film contains an additive element selected from scandium, yttrium or erbium. A workpiece is placed upon a platen within a plasma chamber. The workpiece includes a substrate having an additive-containing aluminium nitride film deposited thereon and a mask disposed upon the additive-containing aluminium nitride film, which defines at least one trench. A first etching gas is introduced into the chamber with a first flow rate, a second etching gas is introduced into the chamber with a second flow rate, and a plasma is established within the chamber to etch the additive-containing aluminium nitride film exposed within the trench. The first etching gas comprises boron trichloride and the second etching gas comprises chlorine. A ratio of the first flow rate to the second flow rate is greater than or equal to 1:1.

The current disclosure relates to a method of etching etchable material from a semiconductor substrate is disclosed. Th method comprises providing a substrate comprising the etchable material into a reaction chamber and providing a haloalkylamine into the reaction chamber in vapor phase for etching the etchable material. The disclosure further relates to a semiconductor processing assembly, and to a method of cleaning a reaction chamber.

Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO.sub.2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO.sub.2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

Disclosed herein is an etching method for a workpiece. The etching method includes the steps of dissociating an inert gas to form a plasma in an evacuated condition of a chamber to thereby remove moisture present on the workpiece set in the chamber, and next dissociating a fluorine-based stable gas instead of the inert gas to form a plasma in the chamber after removing the moisture to thereby dry-etch the workpiece.

Improved methods for chemically etching silicon are provided herein. In some embodiments, a method of etching a silicon material includes: (a) exposing the silicon material to a halogen-containing gas; (b) evacuating the halogen-containing gas from the semiconductor processing chamber; (c) exposing the silicon material to an amine vapor to etch a monolayer of the silicon material; (d) evacuating the amine vapor from the semiconductor processing chamber and; (e) optionally repeating (a)-(d) to etch the silicon material to a predetermined thickness.

A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.