A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.

A semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; an ohmic electrode above the substrate; and a contact layer in contact with at least a part of the ohmic electrode, the contact layer containing silicon and chlorine. The second nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer. A two-dimensional electron gas channel is formed in the first nitride semiconductor layer at a heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer. A silicon concentration has a higher peak value than a chlorine concentration in the contact layer.

A first semiconductor layer, a second semiconductor layer, a channel layer, a barrier layer, and a third semiconductor layer are crystal-grown in this order on a first substrate in the +c axis direction, a second substrate is bonded to the side of the barrier layer of the first substrate, and after that, the first substrate is removed, and the first semiconductor layer is selectively thermally decomposed by heating.

Provided are a process gas supply apparatus which supplies a process gas onto a wafer to etch an oxide layer by dividing an edge zone into a first zone and a second zone located outside the first zone and dividing the second zone into a plurality of sub-zones and a wafer treatment system including the process gas supply apparatus.

An exemplary embodiment provides a method which etches a second layer in a base body to be processed having a first layer containing Ni and Si and a second layer containing Si and N which are exposed to a surface thereof. The method according to the exemplary embodiment includes (a) preparing a base body to be processed in a processing chamber, and (b) supplying a first processing gas which contains carbon and fluorine but does not contain oxygen into the processing chamber and generating plasma in the processing chamber.

A high-electron-mobility field effect transistor is formed with a buffer region having a stepped lateral profile, the stepped lateral profile having first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section and including a buried field plate, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections. A barrier region is formed along the stepped lateral profile. The barrier region is separated from the buried field plate by a portion of the buffer region. The buffer region is formed from a first semiconductor material and the barrier region is formed from a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel of a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions.

Methods for evaluating synergy of modification and removal operations for a wide variety of materials to determine process conditions for self-limiting etching by atomic layer etching are provided herein. Methods include determining the surface binding energy of the material, selecting a modification gas for the material where process conditions for modifying a surface of the material generate energy less than the modification energy and greater than the desorption energy, selecting a removal gas where process conditions for removing the modified surface generate energy greater than the desorption energy to remove the modified surface but less than the surface binding energy of the material to prevent sputtering, and calculating synergy to maximize the process window for atomic layer etching.

A method for forming a group III-V semiconductor channel region in a transistor is provided herein. The method includes exposing a substrate including an oxide layer to a first plasma to treat the oxide layer, exposing the treated oxide layer to a second plasma to convert the oxide layer to an evaporable layer, evaporating the evaporable layer to expose a group III-V semiconductor material surface, and exposing the group III-V semiconductor material surface to an oxygen containing gas to oxidize the group III-V semiconductor material. The processes may be repeated until a recessed depth having a predetermined depth is formed. A group III-V semiconductor channel is then formed in the predetermined recessed depth. The control of the height of the group III-V semiconductor channel is improved.

Provided is a method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device includes forming a target etching layer on a substrate, patterning the target etching layer to form a pattern layer including a pattern portion having a first height and a first width and a recess portion having a second width, providing a first gas and a second gas on the pattern layer, and performing a reaction process including reacting the first and second gases with a surface of the pattern portion by irradiating a laser beam on the pattern layer. The performing the reaction process includes removing a portion of sidewalls of the pattern portion so that the pattern portion has a third width that is smaller than the first width.

Disclosed are sulfur-containing compounds for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The plasma etching compounds may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.