Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

A semiconductor device having: a substrate; a nitride semiconductor layer including a first semiconductor layer made of GaN or In.sub.xGa.sub.1-xN (0<x≦1) and formed on the substrate and a second semiconductor layer containing Al and formed on the first semiconductor layer; and a protective film formed on the set of nitride semiconductor layers. The nitride semiconductor layer has an active section and an inactive section surrounding the active section, and a portion of the second semiconductor layer has been removed from the inactive section.

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.

The present disclosure provides a nitride semiconductor device capable of reducing the ohmic contact resistance of a source electrode and a drain electrode with respect to a two-dimensional electron gas. The nitride semiconductor device includes: a first nitride semiconductor layer configured as an electron transportation layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and configured as an electron supply layer, an etch stop layer formed on the second nitride semiconductor layer and formed by a nitride semiconductor material having a bandgap greater than that of the second nitride semiconductor layer, a gate formed on the etch stop layer; and a source electrode and a drain electrode, disposed above the etch stop layer on opposite sides, wherein the gate is between the source electrode and the drain electrode. Lower portions of the source electrode and the drain electrode penetrate the etch stop layer into a middle portion of the second semiconductor layer along a vertical direction.

A high-threshold-voltage normally-off high-electron-mobility transistor (HEMT) includes a nucleation layer and an epitaxial layer are grown sequentially on a substrate; a barrier layer, a source, and a drain above the epitaxial layer; the barrier layer and the epitaxial layer form a heterojunction structure, and the contact interface therebetween is induced by polarization charges to generate two-dimensional electron gas. The HEMT includes a passivation layer above the barrier layer; a gate cap layer above the gate region barrier layer; the upper part of the gate cap layer is subjected to surface plasma oxidation to form an oxide dielectric layer, or a single-layer or multiple gate dielectric insertion layer is directly deposited thereon. The HEMT includes a gate is located above the gate dielectric insertion layer; the gate is in contact with the passivation layer; and a field plate extends from the gate to the drain on the passivation layer.

The present invention discloses a high-linearity GaN-based millimeter wave device and preparation method thereof. The device includes an AlGaN/GaN heterojunction epitaxial layer, the AlGaN/GaN heterojunction epitaxial layer is of a boss structure, a protruding portion above the boss is an active region, two ends of an upper surface of the active region are respectively connected to a source electrode and a drain electrode, p-type GaN regions with different doping concentrations are located between the source electrode and the drain electrode on the upper surface of the active region, wherein the p-type GaN regions with different doping concentrations are formed by arranging a first p-type GaN region and a second p-type GaN region with different doping concentrations and the same thickness front and back along a gate width, a rear surface of the first p-type GaN region coincides with a front surface of the second p-type GaN region, and left and right edges of the first p-type GaN region and the second p-type GaN region are aligned respectively; and a gate electrode is located above the p-type GaN regions with different doping concentrations. The proposed structure of placing p-type GaN regions with different doping concentrations under the gate effectively modulates the threshold voltage of the device and improves the linearity of the device.

A film having film continuity can be formed.

There is provided a technique including: preparing a substrate having a metal-containing film formed on a surface thereof; and slimming the metal-containing film by pulse-supplying a halogen-containing gas to the substrate.

A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.

A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.