The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a bulk substrate having an upper surface, a semiconductor layer above the bulk substrate, an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region on the bulk substrate, the source region and the drain region are raised above the upper surface of the bulk substrate, in which the source region and the drain region include an epitaxial semiconductor material, a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer, and a gate electrode above the gate dielectric.

A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

A semiconductor device includes an isolation structure in a substrate; and a gate structure over an active region of the substrate. The isolation structure surrounds the active region. The gate structure includes a first section parallel to a second section. The semiconductor device further includes a conductive field plate extending between the first section and the second section and overlapping an edge of the active region. A portion of the conductive field plate extends beyond the edge of the active region, The conductive field plate includes a dielectric layer having a first portion and a second portion, and the first portion is thicker than the second portion. The semiconductor device includes a first well overlapping the edge of the active region. The first well extends underneath the isolation structure. The conductive field plate extends beyond an outer-most edge of the first well.

A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.

A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and second fins protruding from the substrate and separated by a trench. The first fin includes first and second portions of the first type on the first region and a third portion of the second type on the second region. A first gate structure surrounds the second portion and the third portion. A first work function adjusting layer is on the gate insulator layer on the first and second portions. A second work function adjusting layer is on the first work function adjusting layer, the gate insulator layer on the third portion, and the first insulator layer. The device also includes a gate on the second work function adjusting layer, a hardmask layer on the gate, and an interlayer dielectric layer surrounding the gate structure.

A method of making an integrated circuit includes forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type. The drain well includes a first zone with a first concentration of the first dopant and a second zone having a second concentration of the first dopant different from the first concentration of the first dopant. The method further includes forming a source well in the substrate, the source well having a second dopant type opposite from the first dopant type, the source well being adjacent to the drift region in the substrate. The method includes forming a gate electrode over a top surface of the substrate over the drift region and the source well, and being laterally separated from the drain well. The method includes forming a drain low-density doped (LDD) region in the second zone of the drain well.

An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.