An organic light emitting diode display device are provided. The organic light emitting diode display device includes: a substrate; a barrier layer, located on a side of the substrate; a first buffer layer, located on a side of the barrier layer; a first semiconductor layer, located on a side of the first buffer layer; a first gate insulating layer, located on a side of the first semiconductor layer; a first gate electrode, located on a side of the first gate insulating layer; a second buffer layer, located on a side of the first gate electrode; a second semiconductor layer, located on a side of the second buffer layer; a second gate insulating layer, located on a side of the second semiconductor layer; a second gate electrode, located on a side of the second gate insulating layer.

Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

A display panel includes a base layer, a first thin film transistor disposed on the base layer and including a silicon semiconductor pattern, a first control electrode is spaced apart from the silicon semiconductor pattern. A first input electrode is connected to a first side of the silicon semiconductor pattern. A first output electrode is connected to a second side of the silicon semiconductor pattern. The display panel includes a second thin film transistor. An organic light emitting diode includes a first electrode connected to the first thin film transistor, a second electrode, and an emission layer. A first insulating layer includes openings exposing the first side and the second side of the silicon semiconductor pattern, respectively. The first input electrode and the first output electrode are positioned in the openings respectively.

Methods for low-temperature formation of one or more thin-film semiconductor structures on a substrate that include the steps of, forming a (poly)silane layer over a substrate, transforming one or more parts of the (poly)silane layer in one or more thin-film solid-state semiconductor structures, by exposing the one or more parts with light from an

Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate. In an embodiment of the disclosure, a poly-silicon layer, a gate insulation layer, and a gate metal layer are formed in sequence on a substrate; the gate metal layer is patterned to form a gate electrode; the gate insulation layer is etched to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and the poly-silicon layer is doped by an ion doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form both a lightly doped area and a heavily doped area.

A thin film transistor (TFT) structure is provided herein, which comprises a substrate, a light-shielding resin, a polysilicon, a gate electrode insulator, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode. The light-shielding resin has functions of light-shielding and insulation. With doping through two through holes at two sides, the manufacturing process is simplified, the exposure process is simplified, the production time is shortened, the usage of masks is decreased, and the production cost is lowered.

An array substrate and a method of manufacturing the same are provided. The array substrate includes a substrate, a plurality of thin film transistors disposed on the substrate, and a planarization layer covering the plurality of thin film transistors and filled a region defined by the plurality of thin film transistors and the substrate.

A display device including a substrate, a gate driver disposed on the substrate and including a plurality of stages, a clock signal line disposed on the substrate, and transmitting a clock signal to at least one of the stages, a transistor disposed on the substrate, and a light blocking layer disposed between the substrate and the transistor and overlapping the transistor. The clock signal line includes a first conductive line and a second conductive line overlapping the first conductive line, and the first conductive line is disposed in the same layer as the light blocking layer.

An LTPS pixel unit and a manufacturing method. The method includes following steps: forming a buffering layer on the substrate; forming a semiconductor pattern and a common electrode pattern which are disposed with an interval on the buffering layer; sequentially forming a first insulation layer, a gate electrode pattern and a second insulation layer on the semiconductor pattern; forming a source electrode pattern and a drain electrode pattern on the second insulation layer, wherein, the source electrode pattern and the drain electrode pattern electrically contact with the semiconductor pattern through a first contact hole at the first insulation layer and the second insulation layer; and forming a pixel electrode pattern on the second insulation layer, wherein, the pixel electrode pattern electrically contacts with the source electrode pattern or the drain electrode pattern. Accordingly, the present invention can save the cost and increase process yield.

A substrate treating apparatus including an unloading order changing unit. The unloading order changing unit reverses an order, in regard to unloading of substrates in a carrier from the top, between a poor inclined substrate and a substrate at least immediately above the poor inclined substrate when the poor inclined substrate is present whose inclination is determined larger than a pre-set threshold by a poor inclination determining unit. That is, the order is reversed such that the poor inclined substrate whose surface may be possibly be scratched with a hand is unloaded prior to the substrate immediately above the poor inclined substrate. Accordingly, this inhibits damages on the substrate caused by scratching a substrate surface with the hand of a substrate transport mechanism.