A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.

An embodiment relates to a device comprising a first section and a second section. The first section comprises a first metal oxide semiconductor (MOS) interface comprising a first portion and a second portion. The first portion comprises a first contact with a horizontal surface of a semiconductor substrate and the second portion comprises a second contact with a trench sidewall of a trench region of the semiconductor substrate. The second section comprises one of a second metal oxide semiconductor (MOS) interface and a metal region. The second MOS interface comprises a third contact with the trench sidewall of the trench region. The metal region comprises a fourth contact with a first conductivity type drift layer. The first section and the second section are located contiguously within the device along a lateral direction.

A semiconductor device includes a silicon carbide semiconductor body. A first shielding region of a first conductivity type is connected to a first contact at a first surface of the silicon carbide semiconductor body. A current spread region of a second conductivity type is connected to a second contact at a second surface of the silicon carbide semiconductor body. A doping concentration profile of the current spread region includes peaks along a vertical direction perpendicular to the first surface. A doping concentration of one peak or one peak-group of the peaks is at least 50% higher than a doping concentration of any other peak of the current spread region. A vertical distance between the one peak or the one peak-group of the current spread region and the first surface is larger than a second vertical distance between the first surface and a maximum doping peak of the first shielding region.

A power semiconductor device includes an active region with power cells, each configured to conduct a load current portion between first and second load terminals. Each power cell includes: trenches and mesas laterally confined by the trenches and in a vertical direction adjoining a drift region. The mesas include an active mesa having a source region of a first conductivity type and a body region of a second conductivity type separating the source region from the drift region. Both the source and body region are electrically connected to the first load terminal. At least one trench adjacent to the active mesa is configured to induce a conductive channel in the active mesa. A punch through structure s electrically separated from the active mesa by at least one separation stack.

A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

The fabrication method for a silicon carbide semiconductor device according to this disclosure includes a step of forming a dielectric film over part of a silicon carbide layer, a step of forming an ohmic electrode adjoining the dielectric film on the silicon carbide layer, a step of removing an oxidized layer on the ohmic electrode, a step of forming a mask with its opening on the side opposite to the side where the ohmic electrode is adjoining the dielectric film on the ohmic electrode having the oxidized layer removed and on the dielectric film, and a step of wet etching of a film to be etched with hydrofluoric acid with the mask formed. With the fabrication method for a silicon carbide semiconductor device described in this disclosure, it is possible to fabricate a silicon carbide semiconductor device with reduced failure.

A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.

A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

A semiconductor device of embodiments includes: a first silicon carbide region of first conductive type including a first region in contact with a first face of a silicon carbide layer having first and second faces; a second silicon carbide region of second conductive type above the first silicon carbide region; a third silicon carbide region of second conductive type above the second silicon carbide region; a fourth silicon carbide region of first conductive type above the second silicon carbide region; a first gate electrode and a second gate electrode extending in the first direction; a first electrode on the first face and including a first portion and a second portion between the first and the second gate electrode. The first portion contacts the third and the fourth silicon carbide region. The second portion provided in the first direction of the first portion and contacts with the first region.

A semiconductor device of embodiments includes: an electrode containing titanium (Ti); a silicon carbide layer; a first region provided between the silicon carbide layer and the electrode, containing silicon (Si) and oxygen (O), and having a thickness equal to or more than 2 nm and equal to or less than 10 nm; and a second region provided between the first region and the electrode and containing titanium (Ti) and silicon (Si).