A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

A low specific on-resistance (R.sub.on,sp) power semiconductor device includes a power device and a transient voltage suppressor (TVS); wherein the power device comprises a gate electrode, a drain electrode, a bulk electrode, a source electrode and a parasitic body diode, the bulk electrode and the source electrode are shorted, the TVS comprises an anode electrode and a cathode electrode, the drain electrode of the power device and the anode electrode of the TVS are connected by a first metal to form a high-voltage terminal electrode, the source electrode of the power device and the cathode electrode of the TVS are connected by a second metal to form a low-voltage terminal electrode.

Provided is a semiconductor apparatus comprising: an emitter region having a first conductivity type provided on a front surface of a semiconductor substrate; a first gate trench part and a second gate trench part in contact with the emitter region; a first emitter non-contact trench part and a second emitter non-contact trench part out of contact with the emitter region; a gate pad for setting the first gate trench part, the second gate trench part, the first emitter non-contact trench part, and the second emitter non-contact trench part to gate potential; and a diode having an anode connected to the gate pad and a cathode connected to the first emitter non-contact trench part and the second emitter non-contact trench part, wherein the first gate trench part, the first emitter non-contact trench part, the second gate trench part, and the second emitter non-contact trench part are adjacently arranged in order.

A power element includes a substrate structure, an insulation layer, a dielectric layer, a transistor, and a plurality of zener diodes. The transistor is located in a transistor formation region of the substrate structure. The plurality of zener diodes are located in a circuit element formation region of the substrate structure and connected in series with each other. Each of the zener diodes includes a zener diode doping structure and a zener diode metal structure. The zener diode doping structure is formed on the insulation layer and is covered by the dielectric layer. The zener diode doping structure includes a P-type doped region and an N-type doped region that are in contact with each other. The zener diode metal structure is formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region.

A composite power element and a method for manufacturing the same are provided. The power element includes a substrate structure, an insulation layer, a dielectric layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The zener diode is formed in a circuit element formation region of the substrate structure, and includes a zener diode doped structure formed on the insulation layer and covered by the dielectric layer. The zener diode doped structure includes a P-type doped region and an N-type doped region. The zener diode includes a zener diode metal structure formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region. The zener diode is configured to receive a reverse bias voltage when the power element is energized.

The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.

A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.

Disclosed is a gate control circuit that generates a gate control signal of an output transistor connected between an application end of a power supply voltage and an application end of an output voltage. The gate control circuit includes a first current source connected between the application end of the power supply voltage and the application end of the output voltage, a second current source connected between an application end of a booster voltage and an application end of a reference voltage, the booster voltage being raised to a voltage value higher than the power supply voltage in a steady state, an output stage that uses at least one of the first and second current sources to generate a gate charge current for charging a gate of the output transistor, and a controller that uses at least one of the first and second current sources according to the output voltage.

Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.