A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A pixel includes: a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a second node, and a second electrode coupled to a third node; a first initialization transistor coupled between the first node and a first initialization voltage line, and including a gate electrode coupled to a scan line, where the first initialization voltage line is configured to supply a first initialization voltage; a first emission control transistor coupled between a fourth node and a fifth node and including a gate electrode coupled to the first node; a second emission control transistor coupled between the third node and the fifth node and including a gate electrode coupled to an emission control line; and a light-emitting element coupled between the fourth node and a driving low voltage line. The driving transistor and the first emission control transistor are different types of transistors.

An exemplary embodiment of the present disclosure provides a display device including: a substrate; a semiconductor layer disposed on the substrate; a first transistor including a first gate electrode disposed on the semiconductor layer; a light-emitting diode connected with the first transistor; and a first layer disposed between the substrate and the semiconductor layer, wherein the semiconductor layer includes a first electrode, a second electrode, and a channel disposed between the first electrode and the second electrode, the channel includes an impurity, and the first layer overlaps the first transistor.

A semiconductor device including a substrate, a polysilicon semiconductor layer, and a conductive wire is provided. The polysilicon semiconductor layer is disposed on the substrate. The conductive wire is disposed on the substrate. The conductive wire contacts the polysilicon semiconductor layer through a contact portion. The polysilicon semiconductor layer and the contact portion of the conductive wire respectively have sides aligned with each other. The semiconductor device of the disclosure has good electrical connection, mitigated contact problems, improved reliability, reduced resistivity, increased driving capability, or improved display quality.

A manufacturing apparatus and a manufacturing method are provided. A manufacturing apparatus includes a chamber, and a stage disposed in the chamber. The stage includes an upper surface on which a target substrate is disposed, a lower surface opposite to the upper surface, a first side surface extending between the upper surface and the lower surface in a first direction, and a second side surface extending between the upper surface and the lower surface in a second direction perpendicular to the first direction. The first side surface is in a round shape, and at least a portion of the first side surface is convex toward an outside of the stage.

Present invention relates to a semiconductor memory device. A semiconductor memory device according to the present invention may comprise: a memory cell array including a plurality of memory cells over a substrate, the plurality of memory cells repeatedly arranged in horizontal direction and a vertical direction, the horizontal direction parallel to a surface of the substrate, the vertical direction perpendicular to the surface of the substrate, a bit line coupled to the memory cells arranged in the vertical direction, and a word line coupled to the memory cells arranged in the horizontal direction, wherein each of the memory cells comprises a capacitor comprising a storage node and a plate node, and the plate nodes of the capacitors are coupled to each other in the vertical direction and are spaced apart from each other in the horizontal direction.

A display device includes: a display unit including a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines, and a plurality of pixel circuits; and a drive circuit configured to drive the first scan lines, the second scan lines, and the data lines. Each of the pixel circuits includes: a light-emitting element; a drive transistor configured to control a magnitude of an electric current that flows through the light-emitting element, the drive transistor being of a first conductivity type; a first compensation transistor having a control terminal connected to an associated one of the first scan lines, the first compensation transistor being of the first conductivity type; and a second compensation transistor having a control terminal connected to an associated one of the second scan lines, the second compensation transistor being of a second conductivity type. The first and second compensation transistors are connected in series and disposed between a control terminal and a conduction terminal of the drive transistor, the conduction terminal leading to the light-emitting element.

A display device includes a light-emitting element including a first electrode, a second electrode, and a light-emitting layer provided between the first electrode and the second electrode, and a drive transistor that drives the light-emitting element, wherein the drive transistor includes a source electrode, a drain electrode, and a semiconductor layer, one of the source electrode and the drain electrode is electrically connected to the first electrode, the semiconductor layer includes a first channel region close to a high-potential side electrode among the source electrode and the drain electrode, and a second channel region separated from the first channel region via a conductive region, and when a direction from the source electrode to the drain electrode is referred to as a channel direction, a length of the first channel region in the channel direction is shorter than a length of the second channel region in the channel direction.

Provided are a driving backplane, a method for manufacturing the same and a display device. The driving backplane includes a substrate, a first gate disposed on a side of the substrate, an active layer disposed on a side of the first gate away from the substrate, and a second gate disposed on a side of the active layer away from the substrate. An orthographic projection of the second gate on the substrate is located in an orthographic projection of the first gate on the substrate, and in a direction parallel to the substrate, an edge of an orthographic projection of the first gate on the substrate extends beyond an edge of the orthographic projection of the second gate on the substrate.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.