A thin film transistor (TFT) substrate comprises a TFT located on a substrate and including a gate electrode, a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer, the gate electrode and the second semiconductor layer vertically stacked, and the first and second semiconductor layers are made of polycrystalline silicon, and wherein the first and second semiconductor layers are electrically connected to each other in series and respectively include first and second channel portions, and at least one of the first and second channel portions has a bent structure in a plan view.

Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

A display panel and a display device are provided. The display panel includes a plurality of light-emitting devices and a pixel driving circuit for driving the light-emitting devices to emit light. By using oxide transistors as a compensation transistor, first initialization transistor, and second initialization transistor in the pixel driving circuit, and using low-temperature polysilicon transistors as other transistors, both low leakage current characteristics of the oxide transistors and high mobility characteristics of the low-temperature polysilicon transistors can be achieved, making the circuit more stable.

The present invention provides a GOA circuit of LTPS semiconductor TFT, employed for forward-backward bidirectional scan transmission, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors and comprises a transmission part (100), a transmission control part (200), an information storage part (300), a data erase part (400), an output control part (500) and an output buffer part (600). The transmission gate is employed to perform the former-latter level transferring signal, and the NOR gate logic unit and the NAND gate logic unit are employed to convert the signals, and the sequence inverter and the inverter are employed to save and transmit the signals to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the LTPS with single type TFT elements, and the problem of TFT leakage of the single type GOA circuit to optimize the performance of the circuit. The ultra narrow frame or frameless designs can be realized.

A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.

This technology relates to an image sensor. The image sensor may include a substrate including a photoelectric conversion element; a pillar formed over the photoelectric conversion element and having a concave-convex sidewall; a channel film formed along a surface of the pillar and for having at least one end coupled to the photoelectric conversion element; and a transfer gate formed over the channel film.

A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region may be in the semiconductor substrate under the buried insulator layer. The at least one polycrystalline active region fill shape is laterally aligned over the polycrystalline isolation region, where provided. Where provided, the polycrystalline isolation region may extend to different depths in the semiconductor substrate.

A thin-film transistor, method of manufacturing the same, and a display apparatus are provided. The thin-film transistor includes a first active layer, a source, a drain, a gate, and a second active layer, the source, the drain, the gate are disposed on the first active layer with spacing, the gate is located between the source and the drain, the second active layer is disposed on the gate, the source, and the drain, the source and the drain are both respectively connected to the first active layer and the second active layer, and the gate is respectively insulated from the first active layer, the second active layer, the source, and the drain. When a voltage is applied to the gate, the source and the drain may be conducting via the first and second active layer. Therefore, a larger current may flow between the source and the drain.

The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

A TFT, OLED display including the same, and manufacturing method thereof are disclosed. In one aspect, the TFT includes a first gate electrode formed over a substrate and a first insulating layer formed over the substrate and the first gate electrode. A semiconductor layer is formed over the first insulating layer, the semiconductor layer at least partially overlapping the first gate electrode. A second insulating layer is formed over the first insulating layer and the semiconductor layer, the first and second insulating layers having a pair of connection holes formed therethrough. A second gate electrode is electrically connected to the first gate electrode via the connection holes, the connection holes respectively exposing portions of the first gate electrode. Source and drain electrodes are formed over a third insulating layer and electrically connected to the semiconductor layer via the contact holes, the contact holes respectively exposing portions of the semiconductor layer.