The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

The present disclosure provides a display panel and a display apparatus. The display panel includes a driving back plate, a driving circuit, a first electrode layer, micro-LEDs, a second electrode layer, and a bonding layer. The first electrode layer on the driving circuit is provided with a first protruding structure, and the second electrode layer under the micro-LEDs is provided with a second protruding structure. The bonding layer is disposed between the first electrode layer and the second electrode layer to alleviate the problem of micro-LEDs falling off.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

A chip packaging structure and a method for preparing the same, and a method for packaging a semiconductor structure are provided, which relate to the technical field of semiconductors, and solve the technical problem of low yield of a chip. The chip packaging structure includes: a chip, an intermediate insulating layer arranged on the chip and a non-conductive adhesive layer arranged on the intermediate insulating layer, where a plurality of conductive pillar bumps are arranged on the chip, and each conductive pillar bump penetrates through the intermediate insulating layer; the intermediate insulating layer is provided with at least one group of holding holes, and the non-conductive adhesive layer fills the holding holes, so that grooves respectively matched with the holding holes are formed in a surface, far away from the intermediate insulating layer, of the non-conductive adhesive layer.

Disclosed herein are a light emitting device package, a backlight unit, an illumination apparatus, and a method of manufacturing a light emitting device package capable of being used for a display application or an illumination application. The light emitting device package includes: a flip-chip type light emitting device having a first terminal and a second terminal installed therebeneath; a substrate having a first electrode formed at one side of an electrode separating space and a second electrode formed at the other side thereof; a first conductive bonding member installed on the first electrode of the substrate so as to be electrically connected to the first terminal of the light emitting device; a second conductive bonding member installed on the second electrode of the substrate so as to be electrically connected to the second terminal of the light emitting device; a reflection encapsulant molded and installed on the substrate so as to form a reflection cup part reflecting light generated in the light emitting device and filled in the electrode separating space to form an electrode separating part; and a filler filled between the reflection cup part and the first and second conductive bonding members.

A method for cohesively connecting a first component of a power semiconductor module to a second component of a power semiconductor module by sintering, the method comprising the steps of: applying a layer of unsintered sinter material to a predetermined bonding surface of the first component, arranging the second component on the surface layer of unsintered sinter material, attaching the second component to the first component by applying pressure and/or temperature on a locally delimited partial area within the predetermined bonding surface, processing the first and/or second component and/or other components of the power semiconductor module, and complete-area sintering of the sinter material.

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.