A method of forming a bonding element including a first transient liquid phase (TLP) bonding element including a first material and a second material, the first material having a higher melting point than the second material, a ratio of a quantity of the first material and the second material in the first TLP bonding element having a first value, and a second TLP bonding element including the first material and the second material, a ratio of a quantity of the first material and the second material in the second TLP bonding element having a second value different from the first value.

Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.

A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 m to 10 m. A method of manufacturing a metal surface with such micropores also is described.

A heat dissipation device may be formed having a planar structure with a first surface and a surface area enhancement structure projecting from or extending into the first surface of the planar structure. In one embodiment, an integrated circuit package may be formed with the heat dissipation device, wherein the heat dissipation device and at least one integrated circuit device are brought into thermal contact with a thermal interface material between the at least one integrated circuit device and the heat dissipation device and wherein the surface area enhancement structure of the heat dissipation device directly contacts the thermal interface material.

Metal-to-metal adhesion joints are described as a manner to hold down micro devices to a carrier substrate within the context of a micro device transfer manufacturing process. In accordance with embodiments, the metal-to-metal adhesion joints must be broken in order to pick up the micro devices from a carrier substrate, resulting in micro devices with nubs protruding from bottom contacts of the micro devices. Once integrated, the micro devices are bonded to a receiving substrate, the nubs may be embedded in a metallic joint, or alternatively be diffused within the metallic joint as interstitial metallic material that is embedded within the metallic joint.

Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

Provided are a semiconductor element bonding apparatus and a semiconductor element bonding method that do not cause a bonding material to protrude and also ensure adhesion, even when there are variations in a thickness of a semiconductor element or a workpiece and even when there are projections and depressions on surfaces. A semiconductor element bonding apparatus includes disposing means for disposing a workpiece and a semiconductor element at positions facing each other, moving means for moving the workpiece or the semiconductor element in a vertical direction, displacement measuring means for measuring displacement of the workpiece or the semiconductor element in the vertical direction, load measuring means for measuring a contact load between the workpiece and the semiconductor element with the bonding material interposed therebetween, and elastic modulus calculating means for calculating an elastic modulus from results of the measurement by the displacement measuring means and the load measuring means.