A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate. The layer can also include a separation layer of unreactive metal or dielectric, and can be patterned. The unreactive metal pattern can create self-aligned device contacts after bonding is completed. The III-V semiconductor material is brought into contact with the thin layer of reactive metal. Bonding is by a low temperature heat treatment under a compressive pressure. The reactive metal and the functional semiconductor material are selected to undergo solid state reaction and form a stable alloy under the low temperature heat treatment without degrading the III-V material. A semiconductor device of the invention includes a functional III-V layer bonded to a rigid substrate via an alloy of a component of the functional III-V layer and a metal that bonds to the rigid substrate.

A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.

A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.

Techniques disclosed herein relate generally to integrating photonic integrated circuits and electronic integrated circuits in a same package. A device includes a semiconductor substrate and a die stack on the semiconductor substrate. The die stack includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die. The PIC die includes a PIC substrate and a photonic integrated circuit formed on the PIC substrate. The EIC die includes an EIC substrate and an electronic integrated circuit formed on the EIC substrate. The EIC die and the PIC die are bonded such that the PIC substrate and the EIC substrate are disposed on opposing sides of the die stack. The PIC substrate is bonded to the semiconductor substrate. The device also includes a cooling plate bonded to the EIC substrate.

Techniques disclosed herein relate generally to integrating photonic integrated circuits and electronic integrated circuits in a same package. A device includes a semiconductor substrate and a die stack on the semiconductor substrate. The die stack includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die. The PIC die includes a PIC substrate and a photonic integrated circuit formed on the PIC substrate. The EIC die includes an EIC substrate and an electronic integrated circuit formed on the EIC substrate. The EIC die and the PIC die are bonded such that the PIC substrate and the EIC substrate are disposed on opposing sides of the die stack. The PIC substrate is bonded to the semiconductor substrate. The device also includes a cooling plate bonded to the EIC substrate.

A method for assembling a first substrate and a second substrate via metal adhesion layers, the method including: depositing, on a surface of each of the first and second substrates, a metal layer with a thickness controlled to limit surface roughness of each of the deposited metal layers to below a roughness threshold; exposing the metal layers deposited on the surface of the first and second substrates to air; directly adhering the first and second substrates by placing the deposited metal adhesion layers in contact, the surface roughness of the contacted layers being that obtained at an end of the depositing. The adhesion can be carried out in the air, at atmospheric pressure and at room temperature, without applying pressure to the assembly of the first and second substrates resulting from directly contacting the deposited metal adhesion layers.

A method for assembling a first substrate and a second substrate via metal adhesion layers, the method including: depositing, on a surface of each of the first and second substrates, a metal layer with a thickness controlled to limit surface roughness of each of the deposited metal layers to below a roughness threshold; exposing the metal layers deposited on the surface of the first and second substrates to air; directly adhering the first and second substrates by placing the deposited metal adhesion layers in contact, the surface roughness of the contacted layers being that obtained at an end of the depositing. The adhesion can be carried out in the air, at atmospheric pressure and at room temperature, without applying pressure to the assembly of the first and second substrates resulting from directly contacting the deposited metal adhesion layers.

A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.