A fingerprint sensing chip packaging method and package are provided. The method includes: providing a cover plate, providing a fingerprint sensing chip, where a fingerprint sensing region and contact pads at periphery of the region are arranged on a front surface of the chip, electrically connecting the contact pads to a back surface of the chip, forming a first conductive structure electrically connected to the contact pads on the back surface of the chip, laminating the front surface of the chip with a back surface of the cover plate, providing a flexible printed circuit, where a second conductive structure is arranged on a back surface of the circuit and an opening is arranged in the circuit, laminating a front surface of the circuit with the back surface of the cover plate, and electrically connecting the first conductive structure to the second conductive structure.

A semiconductor package (1, 1, 1), the package (1, 1, 1) comprising a first substrate (2) comprising at a front cavity side (5) a plurality of cavities (6, 6), each of the cavities (6, 6) having a bottom wall (7) and side walls (8), and having a conductive path (10) forming an electric contact surface (9) located at the inner side of the bottom wall (7) of the cavity (6, 6), a plurality of semiconductor elements (16, 7), each of the semiconductor elements (16, 17) comprising a first electric contact surface (9) on a first side (26) and a second electric contact surface (9) on a second side (28) opposite to the first side (26), wherein at least one of the semiconductor elements (16, 17) is placed within a corresponding cavity (6, 6) at the front cavity side (5) of the first substrate (2), wherein the first electric contact (27) of the semiconductor element (16, 17) and the electric contact surface (9) at the inner side of the bottom wall (7) of the corresponding cavity (6, 6) are electrically conductive bonded in a material-locking manner, and a second substrate (3), the second substrate (3) being attached with a connection side (12, 13) to the front cavity side (5) of the first substrate (2) thereby encapsulating the semiconductor elements (16, 17) located within the corresponding cavities (6, 6) at the front cavity side (5) of the first substrate (2).

A conductive plate includes a first slit formed in the space between a first chip area and a second chip area, a second slit formed in the space between the first chip area and a terminal area, and a third slit formed in the space between the second chip area and the terminal area. The first slit is a continuous line that penetrates through the conductive plate, whereas the second and third slits are continuous lines that do not penetrate through the conductive plate.

An electronic device includes a substrate, a first pad disposed on the substrate and having a first conductive layer and a second conductive layer disposed on the first conductive layer, a first insulating layer disposed on the first conductive layer and having at least one opening exposing a portion of the first conductive layer, and a second pad disposed opposite to the first pad. The second conductive layer is disposed on the first conductive layer in the at least one opening and extends over the at least one opening to be disposed on a portion of the insulating layer. A bottom of the least one opening of the first insulating layer has an arc edge in a top view of the electronic device.

An object is to provide a technique capable of suppressing an occurrence of a non-filled portion. A semiconductor device includes a base plate, a case, and a semiconductor element. The semiconductor element is disposed in a space of the base plate and the case. The semiconductor device includes a lead electrode. The lead electrode is connected to an upper surface of the semiconductor element in the space. The semiconductor device includes a raised portion. The raised portion is disposed on an upper surface of the lead electrode in the space. The semiconductor device includes a sealing resin. The sealing resin seals the semiconductor element and the lead electrode in the space.

A fingerprint sensing chip packaging method and package are provided. The method includes: providing a cover plate, providing a fingerprint sensing chip, where a fingerprint sensing region and contact pads at periphery of the region are arranged on a front surface of the chip, electrically connecting the contact pads to a back surface of the chip, forming a first conductive structure electrically connected to the contact pads on the back surface of the chip, laminating the front surface of the chip with a back surface of the cover plate, providing a flexible printed circuit, where a second conductive structure is arranged on a back surface of the circuit and an opening is arranged in the circuit, laminating a front surface of the circuit with the back surface of the cover plate, and electrically connecting the first conductive structure to the second conductive structure.

An electronic device includes a substrate, a first pad disposed on the peripheral region of the substrate, and a first insulating layer. The first pad has a first conductive layer and a second conductive layer disposed on the first conductive layer. The first insulating layer is disposed on the first conductive layer and has a plurality of openings arranged along a first direction and exposing a portion of the first conductive layer. The second conductive layer of the first pad is disposed on at least a portion of the first insulating layer and electrically connected to the first conductive layer of the first pad through the openings. In a top view of the electronic device, a width of the second conductive layer of the first pad is greater than a width of the first conductive layer of the first pad in a second direction perpendicular to the first direction.

Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including deep trench capacitors are disclosed. An example substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer coupled to the first glass layer, and a deep trench capacitor embedded in the first core.

A semiconductor package includes a logic die that includes a backside power delivery network layer, an interposer die disposed on the logic die, a plurality of memory dies stacked on the interposer die, and a mold layer that covers the interposer die and the memory dies. Each of the logic die and the interposer die has a first width.

A semiconductor device includes a first conductive layer with first and second sections separated in a first direction. A first chip is on the first section and has a first, second and third electrodes. A second chip is on the second section and has a fourth and fifth electrode. A second conductive layer is between the sections of the first conductive layer in the first direction. The second conductive layer has a first connected section to which the second electrode is connected, a second connected section to which to the fifth electrode is connected, and a first clearance portion between the first and second connected sections in the first direction. A third conductive layer is spaced from the first conductive layer and the second conductive layer and is connected to the third electrode.